Liu Zhi Fu [Thu, 3 May 2018 07:48:14 +0000 (15:48 +0800)]
esp32: fix potential PHY calibration bug
1. Add error log if failed to store calibration version/mac/data
2. Change the NVS calibration version/mac/data store sequence
3. Pass the init_data instead of NULL to esp_phy_rf_init() in esp_phy_load_cal_and_init()
Ivan Grokhotkov [Thu, 26 Oct 2017 11:11:47 +0000 (19:11 +0800)]
esp_restart: fix possible race while stalling other CPU, enable WDT early
Previously esp_restart would stall the other CPU before enabling RTC_WDT.
If the other CPU was executing an s32c1i instruction, the lock signal
from CPU to the arbiter would still be held after CPU was stalled. If
the CPU running esp_restart would then try to access the same locked
memory pool, it would be stuck, because lock signal would never be
released.
With this change, esp_restart resets the other CPU before stalling it.
Ideally, we would want to reset the CPU and keep it in reset, but the
hardware doesn't have such feature for PRO_CPU (it is possible to hold
APP_CPU in reset using DPORT register). Given that ROM code will not use
s32c1i in the first few hundred cycles, doing reset and then stall seems
to be safe.
In addition to than, RTC_WDT initialization is moved to the beginning of
the function, to prevent possible lock-up if CPU stalling still has any
issue.
Ivan Grokhotkov [Thu, 26 Oct 2017 10:46:27 +0000 (18:46 +0800)]
soc/rtc: wait for SLOW_CLK cycle when switching CPU clock
Previous implementation waited for 20us after setting
RTC_CNTL_SOC_CLK_SEL_XTL register, using ets_delay_us, assuming that
the CPU was running at XTAL frequency. In reality, clock switch happened
on the next RTC_SLOW_CLK cycle, and CPU could be running at the previous
frequency (for example, 240 MHz) until then.
ets_delay_us would wait for 20 us * 40 cycles per us = 800 CPU cycles
(assuming 40 MHz XTAL; even less with a 26 MHz XTAL).
But if CPU was running at 240 MHz, 800 cycles would pass in just 3.3us,
while SLOW_CLK cycle could happen as much as 1/150kHz = 6.7us after
RTC_CNTL_SOC_CLK_SEL_XTL was set. So the software would not actually wait
long enough for the clock switch to happen, and would disable the PLL
while CPU was still clocked from PLL, leading to a halt.
This implementation uses rtc_clk_wait_for_slow_cycle() function to wait
until the clock switch, removing the need to wait for a fixed number of
CPU cycles.
Ivan Grokhotkov [Thu, 26 Oct 2017 10:33:13 +0000 (18:33 +0800)]
soc/rtc: add a function to wait for slow clock cycle
Some RTC features are synchronized to RTC_SLOW_CLK, so sometimes
software needs to wait for the next slow clock cycle.
This function implements waiting using Timer Group clock calibration
feature.
Ivan Grokhotkov [Wed, 8 Nov 2017 13:45:10 +0000 (21:45 +0800)]
soc/rtc: power down VDDSDIO in deep sleep
If VDDSDIO is controlled by RTC (which is the case when using 1.8V flash
and CONFIG_BOOTLOADER_VDDSDIO_BOOST is enabled), need to allow VDDSDIO
to be controlled by the state machine before going into deep sleep.
Ivan Grokhotkov [Tue, 29 Aug 2017 00:25:41 +0000 (08:25 +0800)]
freertos: make sure xPortGetCoreID is placed into IRAM
In some cases, xPortGetCoreID was not inlined, and ended up in flash.
Since this function is used in many situations when cache is disabled,
that caused exceptions. Adding IRAM attribute to fix that.
Ivan Grokhotkov [Mon, 11 Sep 2017 12:15:27 +0000 (20:15 +0800)]
freertos: place uxTopUsedPriority into DRAM
When debugging crashes caused by flash cache access errors, OpenOCD may
request the value of uxTopUsedPriority when cache is disabled. Placing
it into IRAM to avoid an error in such case.
Ivan Grokhotkov [Mon, 4 Sep 2017 03:54:18 +0000 (11:54 +0800)]
nvs: check CRC of items on full pages
Previously NVS did check CRC values of key-value pairs on the active
page, but the check for full pages was missing. This adds the necessary
check and a test for it.
Ivan Grokhotkov [Mon, 31 Jul 2017 18:24:25 +0000 (02:24 +0800)]
sdmmc: fix reads/writes to/from unaligned buffers
SDMMC hardware treats all buffers as aligned, and ignores 2 LSBs of
addresses written into DMA descriptors. Previously SDMMC host driver
assumed that data buffers passed from SDDMC command layer would be
aligned. However alignment checks were never implemented in the command
layer, as were the checks that the buffer coming from the application
would be in DMA capable memory. Most of the time this was indeed true.
However in some cases FATFS library can pass buffers offset by 2 bytes
from word boundary. “DMA capable” restriction may be broken if pSRAM
support is used.
This change adds buffer checks to the SDMMC host driver (alignment and
DMA capability), so that the host layer will error out for incompatible
buffers. In SDMMC command layer, a check is added to read and write
functions. If an incompatible buffer is passed from the application, new
buffer (512 bytes size) is allocated, and the transfer is performed
using {READ,WRITE}_SINGLE_BLOCK commands.
Tian Hao [Mon, 28 Aug 2017 09:14:49 +0000 (17:14 +0800)]
component/bt : fix btc security storage bug
1. Remove the bond_device global variable.
2. Fix bond_device add cause memory exception
3. Modify the code location.
4. modify thread security
5. remove esp_ble_clear_bond_device_list() API
6. modify esp_ble_get_gond_device_list() to return list immediately, rather than wait event.
7. modify the gatt_security_server demo to show how to remove all the bonded devices.
8. fix some code bugs may cause something error.
9. modify gatt_security_server demo
XiaXiaotian [Fri, 30 Jun 2017 08:18:29 +0000 (16:18 +0800)]
Broadcast IP route based on source IP address.
If destination IP address of the packet is broadcast address, firstly compare
source IP address with the that of each network interface. If it matches,
packet is forwarded from the interface.
mbedtls: Fix memory leak in initial ECDH exchange if OOM/failure occurs
In ecp_mul_comb(), if (!p_eq_g && grp->T == NULL) and ecp_precompute_comb() fails (which can happen due to OOM), then the new array of points T was leaked.
projects / esp-idf / log