From fde64f12d55275d98e3a657bcfcb23620699f55c Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Fri, 31 May 2019 08:23:48 +0000 Subject: [PATCH] [NFC][Codegen] Add/sub constant-folding: add scalar tests too Just for completeness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362208 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../AArch64/addsub-constant-folding.ll | 438 ++++++++--- test/CodeGen/X86/addsub-constant-folding.ll | 697 +++++++++++++++--- 2 files changed, 953 insertions(+), 182 deletions(-) diff --git a/test/CodeGen/AArch64/addsub-constant-folding.ll b/test/CodeGen/AArch64/addsub-constant-folding.ll index 47a236e373b..bb3b2ebe8ec 100644 --- a/test/CodeGen/AArch64/addsub-constant-folding.ll +++ b/test/CodeGen/AArch64/addsub-constant-folding.ll @@ -1,13 +1,43 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s -declare void @use(<4 x i32> %arg) +declare void @use(i32 %arg) +declare void @vec_use(<4 x i32> %arg) ; (x+c1)+c2 -define <4 x i32> @add_const_add_const(<4 x i32> %arg) { +define i32 @add_const_add_const(i32 %arg) { ; CHECK-LABEL: add_const_add_const: ; CHECK: // %bb.0: +; CHECK-NEXT: add w0, w0, #10 // =10 +; CHECK-NEXT: ret + %t0 = add i32 %arg, 8 + %t1 = add i32 %t0, 2 + ret i32 %t1 +} + +define i32 @add_const_add_const_extrause(i32 %arg) { +; CHECK-LABEL: add_const_add_const_extrause: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x19, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w19, -16 +; CHECK-NEXT: mov w19, w0 +; CHECK-NEXT: add w0, w0, #8 // =8 +; CHECK-NEXT: bl use +; CHECK-NEXT: add w0, w19, #10 // =10 +; CHECK-NEXT: ldp x19, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: ret + %t0 = add i32 %arg, 8 + call void @use(i32 %t0) + %t1 = add i32 %t0, 2 + ret i32 %t1 +} + +define <4 x i32> @vec_add_const_add_const(<4 x i32> %arg) { +; CHECK-LABEL: vec_add_const_add_const: +; CHECK: // %bb.0: ; CHECK-NEXT: movi v1.4s, #10 ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret @@ -16,8 +46,8 @@ define <4 x i32> @add_const_add_const(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @add_const_add_const_extrause(<4 x i32> %arg) { -; CHECK-LABEL: add_const_add_const_extrause: +define <4 x i32> @vec_add_const_add_const_extrause(<4 x i32> %arg) { +; CHECK-LABEL: vec_add_const_add_const_extrause: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill @@ -26,7 +56,7 @@ define <4 x i32> @add_const_add_const_extrause(<4 x i32> %arg) { ; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s -; CHECK-NEXT: bl use +; CHECK-NEXT: bl vec_use ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: movi v0.4s, #10 @@ -34,16 +64,16 @@ define <4 x i32> @add_const_add_const_extrause(<4 x i32> %arg) { ; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: ret %t0 = add <4 x i32> %arg, - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = add <4 x i32> %t0, ret <4 x i32> %t1 } -define <4 x i32> @add_const_add_const_nonsplat(<4 x i32> %arg) { -; CHECK-LABEL: add_const_add_const_nonsplat: +define <4 x i32> @vec_add_const_add_const_nonsplat(<4 x i32> %arg) { +; CHECK-LABEL: vec_add_const_add_const_nonsplat: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI2_0 -; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0] +; CHECK-NEXT: adrp x8, .LCPI4_0 +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0] ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret %t0 = add <4 x i32> %arg, @@ -53,9 +83,38 @@ define <4 x i32> @add_const_add_const_nonsplat(<4 x i32> %arg) { ; (x+c1)-c2 -define <4 x i32> @add_const_sub_const(<4 x i32> %arg) { +define i32 @add_const_sub_const(i32 %arg) { ; CHECK-LABEL: add_const_sub_const: ; CHECK: // %bb.0: +; CHECK-NEXT: add w0, w0, #6 // =6 +; CHECK-NEXT: ret + %t0 = add i32 %arg, 8 + %t1 = sub i32 %t0, 2 + ret i32 %t1 +} + +define i32 @add_const_sub_const_extrause(i32 %arg) { +; CHECK-LABEL: add_const_sub_const_extrause: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x19, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w19, -16 +; CHECK-NEXT: mov w19, w0 +; CHECK-NEXT: add w0, w0, #8 // =8 +; CHECK-NEXT: bl use +; CHECK-NEXT: add w0, w19, #6 // =6 +; CHECK-NEXT: ldp x19, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: ret + %t0 = add i32 %arg, 8 + call void @use(i32 %t0) + %t1 = sub i32 %t0, 2 + ret i32 %t1 +} + +define <4 x i32> @vec_add_const_sub_const(<4 x i32> %arg) { +; CHECK-LABEL: vec_add_const_sub_const: +; CHECK: // %bb.0: ; CHECK-NEXT: movi v1.4s, #6 ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret @@ -64,8 +123,8 @@ define <4 x i32> @add_const_sub_const(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) { -; CHECK-LABEL: add_const_sub_const_extrause: +define <4 x i32> @vec_add_const_sub_const_extrause(<4 x i32> %arg) { +; CHECK-LABEL: vec_add_const_sub_const_extrause: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill @@ -74,7 +133,7 @@ define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) { ; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s -; CHECK-NEXT: bl use +; CHECK-NEXT: bl vec_use ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: movi v0.4s, #6 @@ -82,16 +141,16 @@ define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) { ; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: ret %t0 = add <4 x i32> %arg, - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = sub <4 x i32> %t0, ret <4 x i32> %t1 } -define <4 x i32> @add_const_sub_const_nonsplat(<4 x i32> %arg) { -; CHECK-LABEL: add_const_sub_const_nonsplat: +define <4 x i32> @vec_add_const_sub_const_nonsplat(<4 x i32> %arg) { +; CHECK-LABEL: vec_add_const_sub_const_nonsplat: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI5_0 -; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0] +; CHECK-NEXT: adrp x8, .LCPI9_0 +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_0] ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret %t0 = add <4 x i32> %arg, @@ -101,9 +160,40 @@ define <4 x i32> @add_const_sub_const_nonsplat(<4 x i32> %arg) { ; c2-(x+c1) -define <4 x i32> @add_const_const_sub(<4 x i32> %arg) { +define i32 @add_const_const_sub(i32 %arg) { ; CHECK-LABEL: add_const_const_sub: ; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #-6 +; CHECK-NEXT: sub w0, w8, w0 +; CHECK-NEXT: ret + %t0 = add i32 %arg, 8 + %t1 = sub i32 2, %t0 + ret i32 %t1 +} + +define i32 @add_const_const_sub_extrause(i32 %arg) { +; CHECK-LABEL: add_const_const_sub_extrause: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x19, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w19, -16 +; CHECK-NEXT: mov w19, w0 +; CHECK-NEXT: add w0, w0, #8 // =8 +; CHECK-NEXT: bl use +; CHECK-NEXT: mov w8, #-6 +; CHECK-NEXT: sub w0, w8, w19 +; CHECK-NEXT: ldp x19, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: ret + %t0 = add i32 %arg, 8 + call void @use(i32 %t0) + %t1 = sub i32 2, %t0 + ret i32 %t1 +} + +define <4 x i32> @vec_add_const_const_sub(<4 x i32> %arg) { +; CHECK-LABEL: vec_add_const_const_sub: +; CHECK: // %bb.0: ; CHECK-NEXT: mvni v1.4s, #5 ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: ret @@ -112,8 +202,8 @@ define <4 x i32> @add_const_const_sub(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @add_const_const_sub_extrause(<4 x i32> %arg) { -; CHECK-LABEL: add_const_const_sub_extrause: +define <4 x i32> @vec_add_const_const_sub_extrause(<4 x i32> %arg) { +; CHECK-LABEL: vec_add_const_const_sub_extrause: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill @@ -122,7 +212,7 @@ define <4 x i32> @add_const_const_sub_extrause(<4 x i32> %arg) { ; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s -; CHECK-NEXT: bl use +; CHECK-NEXT: bl vec_use ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: mvni v0.4s, #5 @@ -130,16 +220,16 @@ define <4 x i32> @add_const_const_sub_extrause(<4 x i32> %arg) { ; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: ret %t0 = add <4 x i32> %arg, - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = sub <4 x i32> , %t0 ret <4 x i32> %t1 } -define <4 x i32> @add_const_const_sub_nonsplat(<4 x i32> %arg) { -; CHECK-LABEL: add_const_const_sub_nonsplat: +define <4 x i32> @vec_add_const_const_sub_nonsplat(<4 x i32> %arg) { +; CHECK-LABEL: vec_add_const_const_sub_nonsplat: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI8_0 -; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_0] +; CHECK-NEXT: adrp x8, .LCPI14_0 +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0] ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: ret %t0 = add <4 x i32> %arg, @@ -149,9 +239,38 @@ define <4 x i32> @add_const_const_sub_nonsplat(<4 x i32> %arg) { ; (x-c1)+c2 -define <4 x i32> @sub_const_add_const(<4 x i32> %arg) { +define i32 @sub_const_add_const(i32 %arg) { ; CHECK-LABEL: sub_const_add_const: ; CHECK: // %bb.0: +; CHECK-NEXT: sub w0, w0, #6 // =6 +; CHECK-NEXT: ret + %t0 = sub i32 %arg, 8 + %t1 = add i32 %t0, 2 + ret i32 %t1 +} + +define i32 @sub_const_add_const_extrause(i32 %arg) { +; CHECK-LABEL: sub_const_add_const_extrause: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x19, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w19, -16 +; CHECK-NEXT: mov w19, w0 +; CHECK-NEXT: sub w0, w0, #8 // =8 +; CHECK-NEXT: bl use +; CHECK-NEXT: sub w0, w19, #6 // =6 +; CHECK-NEXT: ldp x19, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: ret + %t0 = sub i32 %arg, 8 + call void @use(i32 %t0) + %t1 = add i32 %t0, 2 + ret i32 %t1 +} + +define <4 x i32> @vec_sub_const_add_const(<4 x i32> %arg) { +; CHECK-LABEL: vec_sub_const_add_const: +; CHECK: // %bb.0: ; CHECK-NEXT: mvni v1.4s, #5 ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret @@ -160,8 +279,8 @@ define <4 x i32> @sub_const_add_const(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @sub_const_add_const_extrause(<4 x i32> %arg) { -; CHECK-LABEL: sub_const_add_const_extrause: +define <4 x i32> @vec_sub_const_add_const_extrause(<4 x i32> %arg) { +; CHECK-LABEL: vec_sub_const_add_const_extrause: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill @@ -170,7 +289,7 @@ define <4 x i32> @sub_const_add_const_extrause(<4 x i32> %arg) { ; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s -; CHECK-NEXT: bl use +; CHECK-NEXT: bl vec_use ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: mvni v0.4s, #5 @@ -178,16 +297,16 @@ define <4 x i32> @sub_const_add_const_extrause(<4 x i32> %arg) { ; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: ret %t0 = sub <4 x i32> %arg, - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = add <4 x i32> %t0, ret <4 x i32> %t1 } -define <4 x i32> @sub_const_add_const_nonsplat(<4 x i32> %arg) { -; CHECK-LABEL: sub_const_add_const_nonsplat: +define <4 x i32> @vec_sub_const_add_const_nonsplat(<4 x i32> %arg) { +; CHECK-LABEL: vec_sub_const_add_const_nonsplat: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI11_0 -; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI11_0] +; CHECK-NEXT: adrp x8, .LCPI19_0 +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_0] ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret %t0 = sub <4 x i32> %arg, @@ -197,9 +316,38 @@ define <4 x i32> @sub_const_add_const_nonsplat(<4 x i32> %arg) { ; (x-c1)-c2 -define <4 x i32> @sub_const_sub_const(<4 x i32> %arg) { +define i32 @sub_const_sub_const(i32 %arg) { ; CHECK-LABEL: sub_const_sub_const: ; CHECK: // %bb.0: +; CHECK-NEXT: sub w0, w0, #10 // =10 +; CHECK-NEXT: ret + %t0 = sub i32 %arg, 8 + %t1 = sub i32 %t0, 2 + ret i32 %t1 +} + +define i32 @sub_const_sub_const_extrause(i32 %arg) { +; CHECK-LABEL: sub_const_sub_const_extrause: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x19, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w19, -16 +; CHECK-NEXT: mov w19, w0 +; CHECK-NEXT: sub w0, w0, #8 // =8 +; CHECK-NEXT: bl use +; CHECK-NEXT: sub w0, w19, #10 // =10 +; CHECK-NEXT: ldp x19, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: ret + %t0 = sub i32 %arg, 8 + call void @use(i32 %t0) + %t1 = sub i32 %t0, 2 + ret i32 %t1 +} + +define <4 x i32> @vec_sub_const_sub_const(<4 x i32> %arg) { +; CHECK-LABEL: vec_sub_const_sub_const: +; CHECK: // %bb.0: ; CHECK-NEXT: movi v1.4s, #10 ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret @@ -208,8 +356,8 @@ define <4 x i32> @sub_const_sub_const(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @sub_const_sub_const_extrause(<4 x i32> %arg) { -; CHECK-LABEL: sub_const_sub_const_extrause: +define <4 x i32> @vec_sub_const_sub_const_extrause(<4 x i32> %arg) { +; CHECK-LABEL: vec_sub_const_sub_const_extrause: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill @@ -218,7 +366,7 @@ define <4 x i32> @sub_const_sub_const_extrause(<4 x i32> %arg) { ; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s -; CHECK-NEXT: bl use +; CHECK-NEXT: bl vec_use ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: movi v0.4s, #10 @@ -226,16 +374,16 @@ define <4 x i32> @sub_const_sub_const_extrause(<4 x i32> %arg) { ; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: ret %t0 = sub <4 x i32> %arg, - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = sub <4 x i32> %t0, ret <4 x i32> %t1 } -define <4 x i32> @sub_const_sub_const_nonsplat(<4 x i32> %arg) { -; CHECK-LABEL: sub_const_sub_const_nonsplat: +define <4 x i32> @vec_sub_const_sub_const_nonsplat(<4 x i32> %arg) { +; CHECK-LABEL: vec_sub_const_sub_const_nonsplat: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI14_0 -; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0] +; CHECK-NEXT: adrp x8, .LCPI24_0 +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI24_0] ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret %t0 = sub <4 x i32> %arg, @@ -245,9 +393,40 @@ define <4 x i32> @sub_const_sub_const_nonsplat(<4 x i32> %arg) { ; c2-(x-c1) -define <4 x i32> @sub_const_const_sub(<4 x i32> %arg) { +define i32 @sub_const_const_sub(i32 %arg) { ; CHECK-LABEL: sub_const_const_sub: ; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #10 +; CHECK-NEXT: sub w0, w8, w0 +; CHECK-NEXT: ret + %t0 = sub i32 %arg, 8 + %t1 = sub i32 2, %t0 + ret i32 %t1 +} + +define i32 @sub_const_const_sub_extrause(i32 %arg) { +; CHECK-LABEL: sub_const_const_sub_extrause: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x19, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w19, -16 +; CHECK-NEXT: mov w19, w0 +; CHECK-NEXT: sub w0, w0, #8 // =8 +; CHECK-NEXT: bl use +; CHECK-NEXT: mov w8, #10 +; CHECK-NEXT: sub w0, w8, w19 +; CHECK-NEXT: ldp x19, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: ret + %t0 = sub i32 %arg, 8 + call void @use(i32 %t0) + %t1 = sub i32 2, %t0 + ret i32 %t1 +} + +define <4 x i32> @vec_sub_const_const_sub(<4 x i32> %arg) { +; CHECK-LABEL: vec_sub_const_const_sub: +; CHECK: // %bb.0: ; CHECK-NEXT: movi v1.4s, #10 ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: ret @@ -256,8 +435,8 @@ define <4 x i32> @sub_const_const_sub(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @sub_const_const_sub_extrause(<4 x i32> %arg) { -; CHECK-LABEL: sub_const_const_sub_extrause: +define <4 x i32> @vec_sub_const_const_sub_extrause(<4 x i32> %arg) { +; CHECK-LABEL: vec_sub_const_const_sub_extrause: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill @@ -266,7 +445,7 @@ define <4 x i32> @sub_const_const_sub_extrause(<4 x i32> %arg) { ; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill -; CHECK-NEXT: bl use +; CHECK-NEXT: bl vec_use ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: movi v0.4s, #2 @@ -274,16 +453,16 @@ define <4 x i32> @sub_const_const_sub_extrause(<4 x i32> %arg) { ; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: ret %t0 = sub <4 x i32> %arg, - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = sub <4 x i32> , %t0 ret <4 x i32> %t1 } -define <4 x i32> @sub_const_const_sub_nonsplat(<4 x i32> %arg) { -; CHECK-LABEL: sub_const_const_sub_nonsplat: +define <4 x i32> @vec_sub_const_const_sub_nonsplat(<4 x i32> %arg) { +; CHECK-LABEL: vec_sub_const_const_sub_nonsplat: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI17_0 -; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0] +; CHECK-NEXT: adrp x8, .LCPI29_0 +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI29_0] ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: ret %t0 = sub <4 x i32> %arg, @@ -293,9 +472,41 @@ define <4 x i32> @sub_const_const_sub_nonsplat(<4 x i32> %arg) { ; (c1-x)+c2 -define <4 x i32> @const_sub_add_const(<4 x i32> %arg) { +define i32 @const_sub_add_const(i32 %arg) { ; CHECK-LABEL: const_sub_add_const: ; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #10 +; CHECK-NEXT: sub w0, w8, w0 +; CHECK-NEXT: ret + %t0 = sub i32 8, %arg + %t1 = add i32 %t0, 2 + ret i32 %t1 +} + +define i32 @const_sub_add_const_extrause(i32 %arg) { +; CHECK-LABEL: const_sub_add_const_extrause: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x19, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w19, -16 +; CHECK-NEXT: mov w8, #8 +; CHECK-NEXT: mov w19, w0 +; CHECK-NEXT: sub w0, w8, w0 +; CHECK-NEXT: bl use +; CHECK-NEXT: mov w8, #10 +; CHECK-NEXT: sub w0, w8, w19 +; CHECK-NEXT: ldp x19, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: ret + %t0 = sub i32 8, %arg + call void @use(i32 %t0) + %t1 = add i32 %t0, 2 + ret i32 %t1 +} + +define <4 x i32> @vec_const_sub_add_const(<4 x i32> %arg) { +; CHECK-LABEL: vec_const_sub_add_const: +; CHECK: // %bb.0: ; CHECK-NEXT: movi v1.4s, #10 ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: ret @@ -304,8 +515,8 @@ define <4 x i32> @const_sub_add_const(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @const_sub_add_const_extrause(<4 x i32> %arg) { -; CHECK-LABEL: const_sub_add_const_extrause: +define <4 x i32> @vec_const_sub_add_const_extrause(<4 x i32> %arg) { +; CHECK-LABEL: vec_const_sub_add_const_extrause: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill @@ -314,7 +525,7 @@ define <4 x i32> @const_sub_add_const_extrause(<4 x i32> %arg) { ; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s -; CHECK-NEXT: bl use +; CHECK-NEXT: bl vec_use ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: movi v0.4s, #10 @@ -322,16 +533,16 @@ define <4 x i32> @const_sub_add_const_extrause(<4 x i32> %arg) { ; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: ret %t0 = sub <4 x i32> , %arg - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = add <4 x i32> %t0, ret <4 x i32> %t1 } -define <4 x i32> @const_sub_add_const_nonsplat(<4 x i32> %arg) { -; CHECK-LABEL: const_sub_add_const_nonsplat: +define <4 x i32> @vec_const_sub_add_const_nonsplat(<4 x i32> %arg) { +; CHECK-LABEL: vec_const_sub_add_const_nonsplat: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI20_0 -; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI20_0] +; CHECK-NEXT: adrp x8, .LCPI34_0 +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI34_0] ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: ret %t0 = sub <4 x i32> , %arg @@ -341,9 +552,41 @@ define <4 x i32> @const_sub_add_const_nonsplat(<4 x i32> %arg) { ; (c1-x)-c2 -define <4 x i32> @const_sub_sub_const(<4 x i32> %arg) { +define i32 @const_sub_sub_const(i32 %arg) { ; CHECK-LABEL: const_sub_sub_const: ; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #6 +; CHECK-NEXT: sub w0, w8, w0 +; CHECK-NEXT: ret + %t0 = sub i32 8, %arg + %t1 = sub i32 %t0, 2 + ret i32 %t1 +} + +define i32 @const_sub_sub_const_extrause(i32 %arg) { +; CHECK-LABEL: const_sub_sub_const_extrause: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x19, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w19, -16 +; CHECK-NEXT: mov w8, #8 +; CHECK-NEXT: mov w19, w0 +; CHECK-NEXT: sub w0, w8, w0 +; CHECK-NEXT: bl use +; CHECK-NEXT: mov w8, #6 +; CHECK-NEXT: sub w0, w8, w19 +; CHECK-NEXT: ldp x19, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: ret + %t0 = sub i32 8, %arg + call void @use(i32 %t0) + %t1 = sub i32 %t0, 2 + ret i32 %t1 +} + +define <4 x i32> @vec_const_sub_sub_const(<4 x i32> %arg) { +; CHECK-LABEL: vec_const_sub_sub_const: +; CHECK: // %bb.0: ; CHECK-NEXT: movi v1.4s, #6 ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: ret @@ -352,8 +595,8 @@ define <4 x i32> @const_sub_sub_const(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @const_sub_sub_const_extrause(<4 x i32> %arg) { -; CHECK-LABEL: const_sub_sub_const_extrause: +define <4 x i32> @vec_const_sub_sub_const_extrause(<4 x i32> %arg) { +; CHECK-LABEL: vec_const_sub_sub_const_extrause: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill @@ -362,7 +605,7 @@ define <4 x i32> @const_sub_sub_const_extrause(<4 x i32> %arg) { ; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s -; CHECK-NEXT: bl use +; CHECK-NEXT: bl vec_use ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: movi v0.4s, #6 @@ -370,16 +613,16 @@ define <4 x i32> @const_sub_sub_const_extrause(<4 x i32> %arg) { ; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: ret %t0 = sub <4 x i32> , %arg - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = sub <4 x i32> %t0, ret <4 x i32> %t1 } -define <4 x i32> @const_sub_sub_const_nonsplat(<4 x i32> %arg) { -; CHECK-LABEL: const_sub_sub_const_nonsplat: +define <4 x i32> @vec_const_sub_sub_const_nonsplat(<4 x i32> %arg) { +; CHECK-LABEL: vec_const_sub_sub_const_nonsplat: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI23_0 -; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI23_0] +; CHECK-NEXT: adrp x8, .LCPI39_0 +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI39_0] ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: ret %t0 = sub <4 x i32> , %arg @@ -389,9 +632,40 @@ define <4 x i32> @const_sub_sub_const_nonsplat(<4 x i32> %arg) { ; c2-(c1-x) -define <4 x i32> @const_sub_const_sub(<4 x i32> %arg) { +define i32 @const_sub_const_sub(i32 %arg) { ; CHECK-LABEL: const_sub_const_sub: ; CHECK: // %bb.0: +; CHECK-NEXT: sub w0, w0, #6 // =6 +; CHECK-NEXT: ret + %t0 = sub i32 8, %arg + %t1 = sub i32 2, %t0 + ret i32 %t1 +} + +define i32 @const_sub_const_sub_extrause(i32 %arg) { +; CHECK-LABEL: const_sub_const_sub_extrause: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x19, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w19, -16 +; CHECK-NEXT: mov w8, #8 +; CHECK-NEXT: sub w19, w8, w0 +; CHECK-NEXT: mov w0, w19 +; CHECK-NEXT: bl use +; CHECK-NEXT: mov w8, #2 +; CHECK-NEXT: sub w0, w8, w19 +; CHECK-NEXT: ldp x19, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: ret + %t0 = sub i32 8, %arg + call void @use(i32 %t0) + %t1 = sub i32 2, %t0 + ret i32 %t1 +} + +define <4 x i32> @vec_const_sub_const_sub(<4 x i32> %arg) { +; CHECK-LABEL: vec_const_sub_const_sub: +; CHECK: // %bb.0: ; CHECK-NEXT: mvni v1.4s, #5 ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret @@ -400,8 +674,8 @@ define <4 x i32> @const_sub_const_sub(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @const_sub_const_sub_extrause(<4 x i32> %arg) { -; CHECK-LABEL: const_sub_const_sub_extrause: +define <4 x i32> @vec_const_sub_const_sub_extrause(<4 x i32> %arg) { +; CHECK-LABEL: vec_const_sub_const_sub_extrause: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill @@ -410,7 +684,7 @@ define <4 x i32> @const_sub_const_sub_extrause(<4 x i32> %arg) { ; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill -; CHECK-NEXT: bl use +; CHECK-NEXT: bl vec_use ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: movi v0.4s, #2 @@ -418,16 +692,16 @@ define <4 x i32> @const_sub_const_sub_extrause(<4 x i32> %arg) { ; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: ret %t0 = sub <4 x i32> , %arg - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = sub <4 x i32> , %t0 ret <4 x i32> %t1 } -define <4 x i32> @const_sub_const_sub_nonsplat(<4 x i32> %arg) { -; CHECK-LABEL: const_sub_const_sub_nonsplat: +define <4 x i32> @vec_const_sub_const_sub_nonsplat(<4 x i32> %arg) { +; CHECK-LABEL: vec_const_sub_const_sub_nonsplat: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI26_0 -; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI26_0] +; CHECK-NEXT: adrp x8, .LCPI44_0 +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI44_0] ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret %t0 = sub <4 x i32> , %arg diff --git a/test/CodeGen/X86/addsub-constant-folding.ll b/test/CodeGen/X86/addsub-constant-folding.ll index 3c48494ae39..09cd2bcea96 100644 --- a/test/CodeGen/X86/addsub-constant-folding.ll +++ b/test/CodeGen/X86/addsub-constant-folding.ll @@ -2,18 +2,73 @@ ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,SSE,X86-SSE ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X64,SSE,X64-SSE -declare void @use(<4 x i32> %arg) +declare void @use(i32 %arg) +declare void @vec_use(<4 x i32> %arg) ; (x+c1)+c2 -define <4 x i32> @add_const_add_const(<4 x i32> %arg) { +define i32 @add_const_add_const(i32 %arg) { ; X86-LABEL: add_const_add_const: ; X86: # %bb.0: -; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: addl $10, %eax ; X86-NEXT: retl ; ; X64-LABEL: add_const_add_const: ; X64: # %bb.0: +; X64-NEXT: # kill: def $edi killed $edi def $rdi +; X64-NEXT: leal 10(%rdi), %eax +; X64-NEXT: retq + %t0 = add i32 %arg, 8 + %t1 = add i32 %t0, 2 + ret i32 %t1 +} + +define i32 @add_const_add_const_extrause(i32 %arg) { +; X86-LABEL: add_const_add_const_extrause: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %esi, -8 +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: leal 8(%esi), %eax +; X86-NEXT: pushl %eax +; X86-NEXT: .cfi_adjust_cfa_offset 4 +; X86-NEXT: calll use +; X86-NEXT: addl $4, %esp +; X86-NEXT: .cfi_adjust_cfa_offset -4 +; X86-NEXT: addl $10, %esi +; X86-NEXT: movl %esi, %eax +; X86-NEXT: popl %esi +; X86-NEXT: .cfi_def_cfa_offset 4 +; X86-NEXT: retl +; +; X64-LABEL: add_const_add_const_extrause: +; X64: # %bb.0: +; X64-NEXT: pushq %rbx +; X64-NEXT: .cfi_def_cfa_offset 16 +; X64-NEXT: .cfi_offset %rbx, -16 +; X64-NEXT: movl %edi, %ebx +; X64-NEXT: leal 8(%rbx), %edi +; X64-NEXT: callq use +; X64-NEXT: leal 10(%rbx), %eax +; X64-NEXT: popq %rbx +; X64-NEXT: .cfi_def_cfa_offset 8 +; X64-NEXT: retq + %t0 = add i32 %arg, 8 + call void @use(i32 %t0) + %t1 = add i32 %t0, 2 + ret i32 %t1 +} + +define <4 x i32> @vec_add_const_add_const(<4 x i32> %arg) { +; X86-LABEL: vec_add_const_add_const: +; X86: # %bb.0: +; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 +; X86-NEXT: retl +; +; X64-LABEL: vec_add_const_add_const: +; X64: # %bb.0: ; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: retq %t0 = add <4 x i32> %arg, @@ -21,8 +76,8 @@ define <4 x i32> @add_const_add_const(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @add_const_add_const_extrause(<4 x i32> %arg) { -; X86-LABEL: add_const_add_const_extrause: +define <4 x i32> @vec_add_const_add_const_extrause(<4 x i32> %arg) { +; X86-LABEL: vec_add_const_add_const_extrause: ; X86: # %bb.0: ; X86-NEXT: subl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 32 @@ -30,14 +85,14 @@ define <4 x i32> @add_const_add_const_extrause(<4 x i32> %arg) { ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8] ; X86-NEXT: paddd %xmm1, %xmm0 -; X86-NEXT: calll use +; X86-NEXT: calll vec_use ; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload ; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: addl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl ; -; X64-LABEL: add_const_add_const_extrause: +; X64-LABEL: vec_add_const_add_const_extrause: ; X64: # %bb.0: ; X64-NEXT: subq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 32 @@ -45,25 +100,25 @@ define <4 x i32> @add_const_add_const_extrause(<4 x i32> %arg) { ; X64-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; X64-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8] ; X64-NEXT: paddd %xmm1, %xmm0 -; X64-NEXT: callq use +; X64-NEXT: callq vec_use ; X64-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload ; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: addq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 8 ; X64-NEXT: retq %t0 = add <4 x i32> %arg, - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = add <4 x i32> %t0, ret <4 x i32> %t1 } -define <4 x i32> @add_const_add_const_nonsplat(<4 x i32> %arg) { -; X86-LABEL: add_const_add_const_nonsplat: +define <4 x i32> @vec_add_const_add_const_nonsplat(<4 x i32> %arg) { +; X86-LABEL: vec_add_const_add_const_nonsplat: ; X86: # %bb.0: ; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: add_const_add_const_nonsplat: +; X64-LABEL: vec_add_const_add_const_nonsplat: ; X64: # %bb.0: ; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: retq @@ -74,14 +129,68 @@ define <4 x i32> @add_const_add_const_nonsplat(<4 x i32> %arg) { ; (x+c1)-c2 -define <4 x i32> @add_const_sub_const(<4 x i32> %arg) { +define i32 @add_const_sub_const(i32 %arg) { ; X86-LABEL: add_const_sub_const: ; X86: # %bb.0: -; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: addl $6, %eax ; X86-NEXT: retl ; ; X64-LABEL: add_const_sub_const: ; X64: # %bb.0: +; X64-NEXT: # kill: def $edi killed $edi def $rdi +; X64-NEXT: leal 6(%rdi), %eax +; X64-NEXT: retq + %t0 = add i32 %arg, 8 + %t1 = sub i32 %t0, 2 + ret i32 %t1 +} + +define i32 @add_const_sub_const_extrause(i32 %arg) { +; X86-LABEL: add_const_sub_const_extrause: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %esi, -8 +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: leal 8(%esi), %eax +; X86-NEXT: pushl %eax +; X86-NEXT: .cfi_adjust_cfa_offset 4 +; X86-NEXT: calll use +; X86-NEXT: addl $4, %esp +; X86-NEXT: .cfi_adjust_cfa_offset -4 +; X86-NEXT: addl $6, %esi +; X86-NEXT: movl %esi, %eax +; X86-NEXT: popl %esi +; X86-NEXT: .cfi_def_cfa_offset 4 +; X86-NEXT: retl +; +; X64-LABEL: add_const_sub_const_extrause: +; X64: # %bb.0: +; X64-NEXT: pushq %rbx +; X64-NEXT: .cfi_def_cfa_offset 16 +; X64-NEXT: .cfi_offset %rbx, -16 +; X64-NEXT: movl %edi, %ebx +; X64-NEXT: leal 8(%rbx), %edi +; X64-NEXT: callq use +; X64-NEXT: leal 6(%rbx), %eax +; X64-NEXT: popq %rbx +; X64-NEXT: .cfi_def_cfa_offset 8 +; X64-NEXT: retq + %t0 = add i32 %arg, 8 + call void @use(i32 %t0) + %t1 = sub i32 %t0, 2 + ret i32 %t1 +} + +define <4 x i32> @vec_add_const_sub_const(<4 x i32> %arg) { +; X86-LABEL: vec_add_const_sub_const: +; X86: # %bb.0: +; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 +; X86-NEXT: retl +; +; X64-LABEL: vec_add_const_sub_const: +; X64: # %bb.0: ; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: retq %t0 = add <4 x i32> %arg, @@ -89,8 +198,8 @@ define <4 x i32> @add_const_sub_const(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) { -; X86-LABEL: add_const_sub_const_extrause: +define <4 x i32> @vec_add_const_sub_const_extrause(<4 x i32> %arg) { +; X86-LABEL: vec_add_const_sub_const_extrause: ; X86: # %bb.0: ; X86-NEXT: subl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 32 @@ -98,14 +207,14 @@ define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) { ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8] ; X86-NEXT: paddd %xmm1, %xmm0 -; X86-NEXT: calll use +; X86-NEXT: calll vec_use ; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload ; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: addl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl ; -; X64-LABEL: add_const_sub_const_extrause: +; X64-LABEL: vec_add_const_sub_const_extrause: ; X64: # %bb.0: ; X64-NEXT: subq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 32 @@ -113,25 +222,25 @@ define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) { ; X64-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; X64-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8] ; X64-NEXT: paddd %xmm1, %xmm0 -; X64-NEXT: callq use +; X64-NEXT: callq vec_use ; X64-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload ; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: addq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 8 ; X64-NEXT: retq %t0 = add <4 x i32> %arg, - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = sub <4 x i32> %t0, ret <4 x i32> %t1 } -define <4 x i32> @add_const_sub_const_nonsplat(<4 x i32> %arg) { -; X86-LABEL: add_const_sub_const_nonsplat: +define <4 x i32> @vec_add_const_sub_const_nonsplat(<4 x i32> %arg) { +; X86-LABEL: vec_add_const_sub_const_nonsplat: ; X86: # %bb.0: ; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: add_const_sub_const_nonsplat: +; X64-LABEL: vec_add_const_sub_const_nonsplat: ; X64: # %bb.0: ; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: retq @@ -142,15 +251,70 @@ define <4 x i32> @add_const_sub_const_nonsplat(<4 x i32> %arg) { ; c2-(x+c1) -define <4 x i32> @add_const_const_sub(<4 x i32> %arg) { +define i32 @add_const_const_sub(i32 %arg) { ; X86-LABEL: add_const_const_sub: ; X86: # %bb.0: +; X86-NEXT: movl $-6, %eax +; X86-NEXT: subl {{[0-9]+}}(%esp), %eax +; X86-NEXT: retl +; +; X64-LABEL: add_const_const_sub: +; X64: # %bb.0: +; X64-NEXT: movl $-6, %eax +; X64-NEXT: subl %edi, %eax +; X64-NEXT: retq + %t0 = add i32 %arg, 8 + %t1 = sub i32 2, %t0 + ret i32 %t1 +} + +define i32 @add_const_const_sub_extrause(i32 %arg) { +; X86-LABEL: add_const_const_sub_extrause: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %esi, -8 +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: leal 8(%esi), %eax +; X86-NEXT: pushl %eax +; X86-NEXT: .cfi_adjust_cfa_offset 4 +; X86-NEXT: calll use +; X86-NEXT: addl $4, %esp +; X86-NEXT: .cfi_adjust_cfa_offset -4 +; X86-NEXT: movl $-6, %eax +; X86-NEXT: subl %esi, %eax +; X86-NEXT: popl %esi +; X86-NEXT: .cfi_def_cfa_offset 4 +; X86-NEXT: retl +; +; X64-LABEL: add_const_const_sub_extrause: +; X64: # %bb.0: +; X64-NEXT: pushq %rbx +; X64-NEXT: .cfi_def_cfa_offset 16 +; X64-NEXT: .cfi_offset %rbx, -16 +; X64-NEXT: movl %edi, %ebx +; X64-NEXT: leal 8(%rbx), %edi +; X64-NEXT: callq use +; X64-NEXT: movl $-6, %eax +; X64-NEXT: subl %ebx, %eax +; X64-NEXT: popq %rbx +; X64-NEXT: .cfi_def_cfa_offset 8 +; X64-NEXT: retq + %t0 = add i32 %arg, 8 + call void @use(i32 %t0) + %t1 = sub i32 2, %t0 + ret i32 %t1 +} + +define <4 x i32> @vec_add_const_const_sub(<4 x i32> %arg) { +; X86-LABEL: vec_add_const_const_sub: +; X86: # %bb.0: ; X86-NEXT: movdqa {{.*#+}} xmm1 = [4294967290,4294967290,4294967290,4294967290] ; X86-NEXT: psubd %xmm0, %xmm1 ; X86-NEXT: movdqa %xmm1, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: add_const_const_sub: +; X64-LABEL: vec_add_const_const_sub: ; X64: # %bb.0: ; X64-NEXT: movdqa {{.*#+}} xmm1 = [4294967290,4294967290,4294967290,4294967290] ; X64-NEXT: psubd %xmm0, %xmm1 @@ -161,8 +325,8 @@ define <4 x i32> @add_const_const_sub(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @add_const_const_sub_extrause(<4 x i32> %arg) { -; X86-LABEL: add_const_const_sub_extrause: +define <4 x i32> @vec_add_const_const_sub_extrause(<4 x i32> %arg) { +; X86-LABEL: vec_add_const_const_sub_extrause: ; X86: # %bb.0: ; X86-NEXT: subl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 32 @@ -170,7 +334,7 @@ define <4 x i32> @add_const_const_sub_extrause(<4 x i32> %arg) { ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8] ; X86-NEXT: paddd %xmm1, %xmm0 -; X86-NEXT: calll use +; X86-NEXT: calll vec_use ; X86-NEXT: movdqa {{.*#+}} xmm0 = [4294967290,4294967290,4294967290,4294967290] ; X86-NEXT: movdqu (%esp), %xmm1 # 16-byte Reload ; X86-NEXT: psubd %xmm1, %xmm0 @@ -178,7 +342,7 @@ define <4 x i32> @add_const_const_sub_extrause(<4 x i32> %arg) { ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl ; -; X64-LABEL: add_const_const_sub_extrause: +; X64-LABEL: vec_add_const_const_sub_extrause: ; X64: # %bb.0: ; X64-NEXT: subq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 32 @@ -186,27 +350,27 @@ define <4 x i32> @add_const_const_sub_extrause(<4 x i32> %arg) { ; X64-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; X64-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8] ; X64-NEXT: paddd %xmm1, %xmm0 -; X64-NEXT: callq use +; X64-NEXT: callq vec_use ; X64-NEXT: movdqa {{.*#+}} xmm0 = [4294967290,4294967290,4294967290,4294967290] ; X64-NEXT: psubd (%rsp), %xmm0 # 16-byte Folded Reload ; X64-NEXT: addq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 8 ; X64-NEXT: retq %t0 = add <4 x i32> %arg, - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = sub <4 x i32> , %t0 ret <4 x i32> %t1 } -define <4 x i32> @add_const_const_sub_nonsplat(<4 x i32> %arg) { -; X86-LABEL: add_const_const_sub_nonsplat: +define <4 x i32> @vec_add_const_const_sub_nonsplat(<4 x i32> %arg) { +; X86-LABEL: vec_add_const_const_sub_nonsplat: ; X86: # %bb.0: ; X86-NEXT: movdqa {{.*#+}} xmm1 = <4294967277,u,u,4294967290> ; X86-NEXT: psubd %xmm0, %xmm1 ; X86-NEXT: movdqa %xmm1, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: add_const_const_sub_nonsplat: +; X64-LABEL: vec_add_const_const_sub_nonsplat: ; X64: # %bb.0: ; X64-NEXT: movdqa {{.*#+}} xmm1 = <4294967277,u,u,4294967290> ; X64-NEXT: psubd %xmm0, %xmm1 @@ -219,14 +383,68 @@ define <4 x i32> @add_const_const_sub_nonsplat(<4 x i32> %arg) { ; (x-c1)+c2 -define <4 x i32> @sub_const_add_const(<4 x i32> %arg) { +define i32 @sub_const_add_const(i32 %arg) { ; X86-LABEL: sub_const_add_const: ; X86: # %bb.0: -; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: addl $-6, %eax ; X86-NEXT: retl ; ; X64-LABEL: sub_const_add_const: ; X64: # %bb.0: +; X64-NEXT: # kill: def $edi killed $edi def $rdi +; X64-NEXT: leal -6(%rdi), %eax +; X64-NEXT: retq + %t0 = sub i32 %arg, 8 + %t1 = add i32 %t0, 2 + ret i32 %t1 +} + +define i32 @sub_const_add_const_extrause(i32 %arg) { +; X86-LABEL: sub_const_add_const_extrause: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %esi, -8 +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: leal -8(%esi), %eax +; X86-NEXT: pushl %eax +; X86-NEXT: .cfi_adjust_cfa_offset 4 +; X86-NEXT: calll use +; X86-NEXT: addl $4, %esp +; X86-NEXT: .cfi_adjust_cfa_offset -4 +; X86-NEXT: addl $-6, %esi +; X86-NEXT: movl %esi, %eax +; X86-NEXT: popl %esi +; X86-NEXT: .cfi_def_cfa_offset 4 +; X86-NEXT: retl +; +; X64-LABEL: sub_const_add_const_extrause: +; X64: # %bb.0: +; X64-NEXT: pushq %rbx +; X64-NEXT: .cfi_def_cfa_offset 16 +; X64-NEXT: .cfi_offset %rbx, -16 +; X64-NEXT: movl %edi, %ebx +; X64-NEXT: leal -8(%rbx), %edi +; X64-NEXT: callq use +; X64-NEXT: leal -6(%rbx), %eax +; X64-NEXT: popq %rbx +; X64-NEXT: .cfi_def_cfa_offset 8 +; X64-NEXT: retq + %t0 = sub i32 %arg, 8 + call void @use(i32 %t0) + %t1 = add i32 %t0, 2 + ret i32 %t1 +} + +define <4 x i32> @vec_sub_const_add_const(<4 x i32> %arg) { +; X86-LABEL: vec_sub_const_add_const: +; X86: # %bb.0: +; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 +; X86-NEXT: retl +; +; X64-LABEL: vec_sub_const_add_const: +; X64: # %bb.0: ; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: retq %t0 = sub <4 x i32> %arg, @@ -234,45 +452,45 @@ define <4 x i32> @sub_const_add_const(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @sub_const_add_const_extrause(<4 x i32> %arg) { -; X86-LABEL: sub_const_add_const_extrause: +define <4 x i32> @vec_sub_const_add_const_extrause(<4 x i32> %arg) { +; X86-LABEL: vec_sub_const_add_const_extrause: ; X86: # %bb.0: ; X86-NEXT: subl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 32 ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 -; X86-NEXT: calll use +; X86-NEXT: calll vec_use ; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload ; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: addl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl ; -; X64-LABEL: sub_const_add_const_extrause: +; X64-LABEL: vec_sub_const_add_const_extrause: ; X64: # %bb.0: ; X64-NEXT: subq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; X64-NEXT: psubd {{.*}}(%rip), %xmm0 -; X64-NEXT: callq use +; X64-NEXT: callq vec_use ; X64-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload ; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: addq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 8 ; X64-NEXT: retq %t0 = sub <4 x i32> %arg, - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = add <4 x i32> %t0, ret <4 x i32> %t1 } -define <4 x i32> @sub_const_add_const_nonsplat(<4 x i32> %arg) { -; X86-LABEL: sub_const_add_const_nonsplat: +define <4 x i32> @vec_sub_const_add_const_nonsplat(<4 x i32> %arg) { +; X86-LABEL: vec_sub_const_add_const_nonsplat: ; X86: # %bb.0: ; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: sub_const_add_const_nonsplat: +; X64-LABEL: vec_sub_const_add_const_nonsplat: ; X64: # %bb.0: ; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: retq @@ -283,14 +501,68 @@ define <4 x i32> @sub_const_add_const_nonsplat(<4 x i32> %arg) { ; (x-c1)-c2 -define <4 x i32> @sub_const_sub_const(<4 x i32> %arg) { +define i32 @sub_const_sub_const(i32 %arg) { ; X86-LABEL: sub_const_sub_const: ; X86: # %bb.0: -; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: addl $-10, %eax ; X86-NEXT: retl ; ; X64-LABEL: sub_const_sub_const: ; X64: # %bb.0: +; X64-NEXT: # kill: def $edi killed $edi def $rdi +; X64-NEXT: leal -10(%rdi), %eax +; X64-NEXT: retq + %t0 = sub i32 %arg, 8 + %t1 = sub i32 %t0, 2 + ret i32 %t1 +} + +define i32 @sub_const_sub_const_extrause(i32 %arg) { +; X86-LABEL: sub_const_sub_const_extrause: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %esi, -8 +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: leal -8(%esi), %eax +; X86-NEXT: pushl %eax +; X86-NEXT: .cfi_adjust_cfa_offset 4 +; X86-NEXT: calll use +; X86-NEXT: addl $4, %esp +; X86-NEXT: .cfi_adjust_cfa_offset -4 +; X86-NEXT: addl $-10, %esi +; X86-NEXT: movl %esi, %eax +; X86-NEXT: popl %esi +; X86-NEXT: .cfi_def_cfa_offset 4 +; X86-NEXT: retl +; +; X64-LABEL: sub_const_sub_const_extrause: +; X64: # %bb.0: +; X64-NEXT: pushq %rbx +; X64-NEXT: .cfi_def_cfa_offset 16 +; X64-NEXT: .cfi_offset %rbx, -16 +; X64-NEXT: movl %edi, %ebx +; X64-NEXT: leal -8(%rbx), %edi +; X64-NEXT: callq use +; X64-NEXT: leal -10(%rbx), %eax +; X64-NEXT: popq %rbx +; X64-NEXT: .cfi_def_cfa_offset 8 +; X64-NEXT: retq + %t0 = sub i32 %arg, 8 + call void @use(i32 %t0) + %t1 = sub i32 %t0, 2 + ret i32 %t1 +} + +define <4 x i32> @vec_sub_const_sub_const(<4 x i32> %arg) { +; X86-LABEL: vec_sub_const_sub_const: +; X86: # %bb.0: +; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 +; X86-NEXT: retl +; +; X64-LABEL: vec_sub_const_sub_const: +; X64: # %bb.0: ; X64-NEXT: psubd {{.*}}(%rip), %xmm0 ; X64-NEXT: retq %t0 = sub <4 x i32> %arg, @@ -298,45 +570,45 @@ define <4 x i32> @sub_const_sub_const(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @sub_const_sub_const_extrause(<4 x i32> %arg) { -; X86-LABEL: sub_const_sub_const_extrause: +define <4 x i32> @vec_sub_const_sub_const_extrause(<4 x i32> %arg) { +; X86-LABEL: vec_sub_const_sub_const_extrause: ; X86: # %bb.0: ; X86-NEXT: subl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 32 ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 -; X86-NEXT: calll use +; X86-NEXT: calll vec_use ; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload ; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: addl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl ; -; X64-LABEL: sub_const_sub_const_extrause: +; X64-LABEL: vec_sub_const_sub_const_extrause: ; X64: # %bb.0: ; X64-NEXT: subq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; X64-NEXT: psubd {{.*}}(%rip), %xmm0 -; X64-NEXT: callq use +; X64-NEXT: callq vec_use ; X64-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload ; X64-NEXT: psubd {{.*}}(%rip), %xmm0 ; X64-NEXT: addq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 8 ; X64-NEXT: retq %t0 = sub <4 x i32> %arg, - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = sub <4 x i32> %t0, ret <4 x i32> %t1 } -define <4 x i32> @sub_const_sub_const_nonsplat(<4 x i32> %arg) { -; X86-LABEL: sub_const_sub_const_nonsplat: +define <4 x i32> @vec_sub_const_sub_const_nonsplat(<4 x i32> %arg) { +; X86-LABEL: vec_sub_const_sub_const_nonsplat: ; X86: # %bb.0: ; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: sub_const_sub_const_nonsplat: +; X64-LABEL: vec_sub_const_sub_const_nonsplat: ; X64: # %bb.0: ; X64-NEXT: psubd {{.*}}(%rip), %xmm0 ; X64-NEXT: retq @@ -347,15 +619,70 @@ define <4 x i32> @sub_const_sub_const_nonsplat(<4 x i32> %arg) { ; c2-(x-c1) -define <4 x i32> @sub_const_const_sub(<4 x i32> %arg) { +define i32 @sub_const_const_sub(i32 %arg) { ; X86-LABEL: sub_const_const_sub: ; X86: # %bb.0: +; X86-NEXT: movl $10, %eax +; X86-NEXT: subl {{[0-9]+}}(%esp), %eax +; X86-NEXT: retl +; +; X64-LABEL: sub_const_const_sub: +; X64: # %bb.0: +; X64-NEXT: movl $10, %eax +; X64-NEXT: subl %edi, %eax +; X64-NEXT: retq + %t0 = sub i32 %arg, 8 + %t1 = sub i32 2, %t0 + ret i32 %t1 +} + +define i32 @sub_const_const_sub_extrause(i32 %arg) { +; X86-LABEL: sub_const_const_sub_extrause: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %esi, -8 +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: leal -8(%esi), %eax +; X86-NEXT: pushl %eax +; X86-NEXT: .cfi_adjust_cfa_offset 4 +; X86-NEXT: calll use +; X86-NEXT: addl $4, %esp +; X86-NEXT: .cfi_adjust_cfa_offset -4 +; X86-NEXT: movl $10, %eax +; X86-NEXT: subl %esi, %eax +; X86-NEXT: popl %esi +; X86-NEXT: .cfi_def_cfa_offset 4 +; X86-NEXT: retl +; +; X64-LABEL: sub_const_const_sub_extrause: +; X64: # %bb.0: +; X64-NEXT: pushq %rbx +; X64-NEXT: .cfi_def_cfa_offset 16 +; X64-NEXT: .cfi_offset %rbx, -16 +; X64-NEXT: movl %edi, %ebx +; X64-NEXT: leal -8(%rbx), %edi +; X64-NEXT: callq use +; X64-NEXT: movl $10, %eax +; X64-NEXT: subl %ebx, %eax +; X64-NEXT: popq %rbx +; X64-NEXT: .cfi_def_cfa_offset 8 +; X64-NEXT: retq + %t0 = sub i32 %arg, 8 + call void @use(i32 %t0) + %t1 = sub i32 2, %t0 + ret i32 %t1 +} + +define <4 x i32> @vec_sub_const_const_sub(<4 x i32> %arg) { +; X86-LABEL: vec_sub_const_const_sub: +; X86: # %bb.0: ; X86-NEXT: movdqa {{.*#+}} xmm1 = [10,10,10,10] ; X86-NEXT: psubd %xmm0, %xmm1 ; X86-NEXT: movdqa %xmm1, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: sub_const_const_sub: +; X64-LABEL: vec_sub_const_const_sub: ; X64: # %bb.0: ; X64-NEXT: movdqa {{.*#+}} xmm1 = [10,10,10,10] ; X64-NEXT: psubd %xmm0, %xmm1 @@ -366,14 +693,14 @@ define <4 x i32> @sub_const_const_sub(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @sub_const_const_sub_extrause(<4 x i32> %arg) { -; X86-LABEL: sub_const_const_sub_extrause: +define <4 x i32> @vec_sub_const_const_sub_extrause(<4 x i32> %arg) { +; X86-LABEL: vec_sub_const_const_sub_extrause: ; X86: # %bb.0: ; X86-NEXT: subl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 32 ; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill -; X86-NEXT: calll use +; X86-NEXT: calll vec_use ; X86-NEXT: movdqa {{.*#+}} xmm0 = [2,2,2,2] ; X86-NEXT: movdqu (%esp), %xmm1 # 16-byte Reload ; X86-NEXT: psubd %xmm1, %xmm0 @@ -381,33 +708,33 @@ define <4 x i32> @sub_const_const_sub_extrause(<4 x i32> %arg) { ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl ; -; X64-LABEL: sub_const_const_sub_extrause: +; X64-LABEL: vec_sub_const_const_sub_extrause: ; X64: # %bb.0: ; X64-NEXT: subq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: psubd {{.*}}(%rip), %xmm0 ; X64-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill -; X64-NEXT: callq use +; X64-NEXT: callq vec_use ; X64-NEXT: movdqa {{.*#+}} xmm0 = [2,2,2,2] ; X64-NEXT: psubd (%rsp), %xmm0 # 16-byte Folded Reload ; X64-NEXT: addq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 8 ; X64-NEXT: retq %t0 = sub <4 x i32> %arg, - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = sub <4 x i32> , %t0 ret <4 x i32> %t1 } -define <4 x i32> @sub_const_const_sub_nonsplat(<4 x i32> %arg) { -; X86-LABEL: sub_const_const_sub_nonsplat: +define <4 x i32> @vec_sub_const_const_sub_nonsplat(<4 x i32> %arg) { +; X86-LABEL: vec_sub_const_const_sub_nonsplat: ; X86: # %bb.0: ; X86-NEXT: movdqa {{.*#+}} xmm1 = <23,u,u,10> ; X86-NEXT: psubd %xmm0, %xmm1 ; X86-NEXT: movdqa %xmm1, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: sub_const_const_sub_nonsplat: +; X64-LABEL: vec_sub_const_const_sub_nonsplat: ; X64: # %bb.0: ; X64-NEXT: movdqa {{.*#+}} xmm1 = <23,u,u,10> ; X64-NEXT: psubd %xmm0, %xmm1 @@ -420,15 +747,72 @@ define <4 x i32> @sub_const_const_sub_nonsplat(<4 x i32> %arg) { ; (c1-x)+c2 -define <4 x i32> @const_sub_add_const(<4 x i32> %arg) { +define i32 @const_sub_add_const(i32 %arg) { ; X86-LABEL: const_sub_add_const: ; X86: # %bb.0: +; X86-NEXT: movl $10, %eax +; X86-NEXT: subl {{[0-9]+}}(%esp), %eax +; X86-NEXT: retl +; +; X64-LABEL: const_sub_add_const: +; X64: # %bb.0: +; X64-NEXT: movl $10, %eax +; X64-NEXT: subl %edi, %eax +; X64-NEXT: retq + %t0 = sub i32 8, %arg + %t1 = add i32 %t0, 2 + ret i32 %t1 +} + +define i32 @const_sub_add_const_extrause(i32 %arg) { +; X86-LABEL: const_sub_add_const_extrause: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %esi, -8 +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl $8, %eax +; X86-NEXT: subl %esi, %eax +; X86-NEXT: pushl %eax +; X86-NEXT: .cfi_adjust_cfa_offset 4 +; X86-NEXT: calll use +; X86-NEXT: addl $4, %esp +; X86-NEXT: .cfi_adjust_cfa_offset -4 +; X86-NEXT: movl $10, %eax +; X86-NEXT: subl %esi, %eax +; X86-NEXT: popl %esi +; X86-NEXT: .cfi_def_cfa_offset 4 +; X86-NEXT: retl +; +; X64-LABEL: const_sub_add_const_extrause: +; X64: # %bb.0: +; X64-NEXT: pushq %rbx +; X64-NEXT: .cfi_def_cfa_offset 16 +; X64-NEXT: .cfi_offset %rbx, -16 +; X64-NEXT: movl %edi, %ebx +; X64-NEXT: movl $8, %edi +; X64-NEXT: subl %ebx, %edi +; X64-NEXT: callq use +; X64-NEXT: movl $10, %eax +; X64-NEXT: subl %ebx, %eax +; X64-NEXT: popq %rbx +; X64-NEXT: .cfi_def_cfa_offset 8 +; X64-NEXT: retq + %t0 = sub i32 8, %arg + call void @use(i32 %t0) + %t1 = add i32 %t0, 2 + ret i32 %t1 +} + +define <4 x i32> @vec_const_sub_add_const(<4 x i32> %arg) { +; X86-LABEL: vec_const_sub_add_const: +; X86: # %bb.0: ; X86-NEXT: movdqa {{.*#+}} xmm1 = [10,10,10,10] ; X86-NEXT: psubd %xmm0, %xmm1 ; X86-NEXT: movdqa %xmm1, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: const_sub_add_const: +; X64-LABEL: vec_const_sub_add_const: ; X64: # %bb.0: ; X64-NEXT: movdqa {{.*#+}} xmm1 = [10,10,10,10] ; X64-NEXT: psubd %xmm0, %xmm1 @@ -439,8 +823,8 @@ define <4 x i32> @const_sub_add_const(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @const_sub_add_const_extrause(<4 x i32> %arg) { -; X86-LABEL: const_sub_add_const_extrause: +define <4 x i32> @vec_const_sub_add_const_extrause(<4 x i32> %arg) { +; X86-LABEL: vec_const_sub_add_const_extrause: ; X86: # %bb.0: ; X86-NEXT: subl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 32 @@ -448,7 +832,7 @@ define <4 x i32> @const_sub_add_const_extrause(<4 x i32> %arg) { ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8] ; X86-NEXT: psubd %xmm1, %xmm0 -; X86-NEXT: calll use +; X86-NEXT: calll vec_use ; X86-NEXT: movdqa {{.*#+}} xmm0 = [10,10,10,10] ; X86-NEXT: movdqu (%esp), %xmm1 # 16-byte Reload ; X86-NEXT: psubd %xmm1, %xmm0 @@ -456,7 +840,7 @@ define <4 x i32> @const_sub_add_const_extrause(<4 x i32> %arg) { ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl ; -; X64-LABEL: const_sub_add_const_extrause: +; X64-LABEL: vec_const_sub_add_const_extrause: ; X64: # %bb.0: ; X64-NEXT: subq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 32 @@ -464,27 +848,27 @@ define <4 x i32> @const_sub_add_const_extrause(<4 x i32> %arg) { ; X64-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; X64-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8] ; X64-NEXT: psubd %xmm1, %xmm0 -; X64-NEXT: callq use +; X64-NEXT: callq vec_use ; X64-NEXT: movdqa {{.*#+}} xmm0 = [10,10,10,10] ; X64-NEXT: psubd (%rsp), %xmm0 # 16-byte Folded Reload ; X64-NEXT: addq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 8 ; X64-NEXT: retq %t0 = sub <4 x i32> , %arg - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = add <4 x i32> %t0, ret <4 x i32> %t1 } -define <4 x i32> @const_sub_add_const_nonsplat(<4 x i32> %arg) { -; X86-LABEL: const_sub_add_const_nonsplat: +define <4 x i32> @vec_const_sub_add_const_nonsplat(<4 x i32> %arg) { +; X86-LABEL: vec_const_sub_add_const_nonsplat: ; X86: # %bb.0: ; X86-NEXT: movdqa {{.*#+}} xmm1 = <23,u,u,10> ; X86-NEXT: psubd %xmm0, %xmm1 ; X86-NEXT: movdqa %xmm1, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: const_sub_add_const_nonsplat: +; X64-LABEL: vec_const_sub_add_const_nonsplat: ; X64: # %bb.0: ; X64-NEXT: movdqa {{.*#+}} xmm1 = <23,u,u,10> ; X64-NEXT: psubd %xmm0, %xmm1 @@ -497,15 +881,72 @@ define <4 x i32> @const_sub_add_const_nonsplat(<4 x i32> %arg) { ; (c1-x)-c2 -define <4 x i32> @const_sub_sub_const(<4 x i32> %arg) { +define i32 @const_sub_sub_const(i32 %arg) { ; X86-LABEL: const_sub_sub_const: ; X86: # %bb.0: +; X86-NEXT: movl $6, %eax +; X86-NEXT: subl {{[0-9]+}}(%esp), %eax +; X86-NEXT: retl +; +; X64-LABEL: const_sub_sub_const: +; X64: # %bb.0: +; X64-NEXT: movl $6, %eax +; X64-NEXT: subl %edi, %eax +; X64-NEXT: retq + %t0 = sub i32 8, %arg + %t1 = sub i32 %t0, 2 + ret i32 %t1 +} + +define i32 @const_sub_sub_const_extrause(i32 %arg) { +; X86-LABEL: const_sub_sub_const_extrause: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %esi, -8 +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl $8, %eax +; X86-NEXT: subl %esi, %eax +; X86-NEXT: pushl %eax +; X86-NEXT: .cfi_adjust_cfa_offset 4 +; X86-NEXT: calll use +; X86-NEXT: addl $4, %esp +; X86-NEXT: .cfi_adjust_cfa_offset -4 +; X86-NEXT: movl $6, %eax +; X86-NEXT: subl %esi, %eax +; X86-NEXT: popl %esi +; X86-NEXT: .cfi_def_cfa_offset 4 +; X86-NEXT: retl +; +; X64-LABEL: const_sub_sub_const_extrause: +; X64: # %bb.0: +; X64-NEXT: pushq %rbx +; X64-NEXT: .cfi_def_cfa_offset 16 +; X64-NEXT: .cfi_offset %rbx, -16 +; X64-NEXT: movl %edi, %ebx +; X64-NEXT: movl $8, %edi +; X64-NEXT: subl %ebx, %edi +; X64-NEXT: callq use +; X64-NEXT: movl $6, %eax +; X64-NEXT: subl %ebx, %eax +; X64-NEXT: popq %rbx +; X64-NEXT: .cfi_def_cfa_offset 8 +; X64-NEXT: retq + %t0 = sub i32 8, %arg + call void @use(i32 %t0) + %t1 = sub i32 %t0, 2 + ret i32 %t1 +} + +define <4 x i32> @vec_const_sub_sub_const(<4 x i32> %arg) { +; X86-LABEL: vec_const_sub_sub_const: +; X86: # %bb.0: ; X86-NEXT: movdqa {{.*#+}} xmm1 = [6,6,6,6] ; X86-NEXT: psubd %xmm0, %xmm1 ; X86-NEXT: movdqa %xmm1, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: const_sub_sub_const: +; X64-LABEL: vec_const_sub_sub_const: ; X64: # %bb.0: ; X64-NEXT: movdqa {{.*#+}} xmm1 = [6,6,6,6] ; X64-NEXT: psubd %xmm0, %xmm1 @@ -516,8 +957,8 @@ define <4 x i32> @const_sub_sub_const(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @const_sub_sub_const_extrause(<4 x i32> %arg) { -; X86-LABEL: const_sub_sub_const_extrause: +define <4 x i32> @vec_const_sub_sub_const_extrause(<4 x i32> %arg) { +; X86-LABEL: vec_const_sub_sub_const_extrause: ; X86: # %bb.0: ; X86-NEXT: subl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 32 @@ -525,7 +966,7 @@ define <4 x i32> @const_sub_sub_const_extrause(<4 x i32> %arg) { ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8] ; X86-NEXT: psubd %xmm1, %xmm0 -; X86-NEXT: calll use +; X86-NEXT: calll vec_use ; X86-NEXT: movdqa {{.*#+}} xmm0 = [6,6,6,6] ; X86-NEXT: movdqu (%esp), %xmm1 # 16-byte Reload ; X86-NEXT: psubd %xmm1, %xmm0 @@ -533,7 +974,7 @@ define <4 x i32> @const_sub_sub_const_extrause(<4 x i32> %arg) { ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl ; -; X64-LABEL: const_sub_sub_const_extrause: +; X64-LABEL: vec_const_sub_sub_const_extrause: ; X64: # %bb.0: ; X64-NEXT: subq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 32 @@ -541,27 +982,27 @@ define <4 x i32> @const_sub_sub_const_extrause(<4 x i32> %arg) { ; X64-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; X64-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8] ; X64-NEXT: psubd %xmm1, %xmm0 -; X64-NEXT: callq use +; X64-NEXT: callq vec_use ; X64-NEXT: movdqa {{.*#+}} xmm0 = [6,6,6,6] ; X64-NEXT: psubd (%rsp), %xmm0 # 16-byte Folded Reload ; X64-NEXT: addq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 8 ; X64-NEXT: retq %t0 = sub <4 x i32> , %arg - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = sub <4 x i32> %t0, ret <4 x i32> %t1 } -define <4 x i32> @const_sub_sub_const_nonsplat(<4 x i32> %arg) { -; X86-LABEL: const_sub_sub_const_nonsplat: +define <4 x i32> @vec_const_sub_sub_const_nonsplat(<4 x i32> %arg) { +; X86-LABEL: vec_const_sub_sub_const_nonsplat: ; X86: # %bb.0: ; X86-NEXT: movdqa {{.*#+}} xmm1 = <19,u,u,6> ; X86-NEXT: psubd %xmm0, %xmm1 ; X86-NEXT: movdqa %xmm1, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: const_sub_sub_const_nonsplat: +; X64-LABEL: vec_const_sub_sub_const_nonsplat: ; X64: # %bb.0: ; X64-NEXT: movdqa {{.*#+}} xmm1 = <19,u,u,6> ; X64-NEXT: psubd %xmm0, %xmm1 @@ -574,14 +1015,70 @@ define <4 x i32> @const_sub_sub_const_nonsplat(<4 x i32> %arg) { ; c2-(c1-x) -define <4 x i32> @const_sub_const_sub(<4 x i32> %arg) { +define i32 @const_sub_const_sub(i32 %arg) { ; X86-LABEL: const_sub_const_sub: ; X86: # %bb.0: -; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: addl $-6, %eax ; X86-NEXT: retl ; ; X64-LABEL: const_sub_const_sub: ; X64: # %bb.0: +; X64-NEXT: # kill: def $edi killed $edi def $rdi +; X64-NEXT: leal -6(%rdi), %eax +; X64-NEXT: retq + %t0 = sub i32 8, %arg + %t1 = sub i32 2, %t0 + ret i32 %t1 +} + +define i32 @const_sub_const_sub_extrause(i32 %arg) { +; X86-LABEL: const_sub_const_sub_extrause: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %esi, -8 +; X86-NEXT: movl $8, %esi +; X86-NEXT: subl {{[0-9]+}}(%esp), %esi +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_adjust_cfa_offset 4 +; X86-NEXT: calll use +; X86-NEXT: addl $4, %esp +; X86-NEXT: .cfi_adjust_cfa_offset -4 +; X86-NEXT: movl $2, %eax +; X86-NEXT: subl %esi, %eax +; X86-NEXT: popl %esi +; X86-NEXT: .cfi_def_cfa_offset 4 +; X86-NEXT: retl +; +; X64-LABEL: const_sub_const_sub_extrause: +; X64: # %bb.0: +; X64-NEXT: pushq %rbx +; X64-NEXT: .cfi_def_cfa_offset 16 +; X64-NEXT: .cfi_offset %rbx, -16 +; X64-NEXT: movl $8, %ebx +; X64-NEXT: subl %edi, %ebx +; X64-NEXT: movl %ebx, %edi +; X64-NEXT: callq use +; X64-NEXT: movl $2, %eax +; X64-NEXT: subl %ebx, %eax +; X64-NEXT: popq %rbx +; X64-NEXT: .cfi_def_cfa_offset 8 +; X64-NEXT: retq + %t0 = sub i32 8, %arg + call void @use(i32 %t0) + %t1 = sub i32 2, %t0 + ret i32 %t1 +} + +define <4 x i32> @vec_const_sub_const_sub(<4 x i32> %arg) { +; X86-LABEL: vec_const_sub_const_sub: +; X86: # %bb.0: +; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 +; X86-NEXT: retl +; +; X64-LABEL: vec_const_sub_const_sub: +; X64: # %bb.0: ; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: retq %t0 = sub <4 x i32> , %arg @@ -589,8 +1086,8 @@ define <4 x i32> @const_sub_const_sub(<4 x i32> %arg) { ret <4 x i32> %t1 } -define <4 x i32> @const_sub_const_sub_extrause(<4 x i32> %arg) { -; X86-LABEL: const_sub_const_sub_extrause: +define <4 x i32> @vec_const_sub_const_sub_extrause(<4 x i32> %arg) { +; X86-LABEL: vec_const_sub_const_sub_extrause: ; X86: # %bb.0: ; X86-NEXT: subl $28, %esp ; X86-NEXT: .cfi_def_cfa_offset 32 @@ -598,7 +1095,7 @@ define <4 x i32> @const_sub_const_sub_extrause(<4 x i32> %arg) { ; X86-NEXT: psubd %xmm0, %xmm1 ; X86-NEXT: movdqu %xmm1, (%esp) # 16-byte Spill ; X86-NEXT: movdqa %xmm1, %xmm0 -; X86-NEXT: calll use +; X86-NEXT: calll vec_use ; X86-NEXT: movdqa {{.*#+}} xmm0 = [2,2,2,2] ; X86-NEXT: movdqu (%esp), %xmm1 # 16-byte Reload ; X86-NEXT: psubd %xmm1, %xmm0 @@ -606,7 +1103,7 @@ define <4 x i32> @const_sub_const_sub_extrause(<4 x i32> %arg) { ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl ; -; X64-LABEL: const_sub_const_sub_extrause: +; X64-LABEL: vec_const_sub_const_sub_extrause: ; X64: # %bb.0: ; X64-NEXT: subq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 32 @@ -614,25 +1111,25 @@ define <4 x i32> @const_sub_const_sub_extrause(<4 x i32> %arg) { ; X64-NEXT: psubd %xmm0, %xmm1 ; X64-NEXT: movdqa %xmm1, (%rsp) # 16-byte Spill ; X64-NEXT: movdqa %xmm1, %xmm0 -; X64-NEXT: callq use +; X64-NEXT: callq vec_use ; X64-NEXT: movdqa {{.*#+}} xmm0 = [2,2,2,2] ; X64-NEXT: psubd (%rsp), %xmm0 # 16-byte Folded Reload ; X64-NEXT: addq $24, %rsp ; X64-NEXT: .cfi_def_cfa_offset 8 ; X64-NEXT: retq %t0 = sub <4 x i32> , %arg - call void @use(<4 x i32> %t0) + call void @vec_use(<4 x i32> %t0) %t1 = sub <4 x i32> , %t0 ret <4 x i32> %t1 } -define <4 x i32> @const_sub_const_sub_nonsplat(<4 x i32> %arg) { -; X86-LABEL: const_sub_const_sub_nonsplat: +define <4 x i32> @vec_const_sub_const_sub_nonsplat(<4 x i32> %arg) { +; X86-LABEL: vec_const_sub_const_sub_nonsplat: ; X86: # %bb.0: ; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: retl ; -; X64-LABEL: const_sub_const_sub_nonsplat: +; X64-LABEL: vec_const_sub_const_sub_nonsplat: ; X64: # %bb.0: ; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: retq -- 2.50.1