From fb0a468b49cb537a507553e3e4221078b2351557 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Sat, 15 Jun 2019 16:12:05 +0000 Subject: [PATCH] [NFC][MCA][X86] Add baseline test coverage for AMD Barcelona (aka K10, fam10h) Looking into sched model for that CPU ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363497 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../X86/Barcelona/clear-super-register-1.s | 63 + .../X86/Barcelona/dependency-breaking-cmp.s | 70 + .../Barcelona/dependency-breaking-pcmpeq.s | 107 + .../Barcelona/dependency-breaking-pcmpgt.s | 108 + .../X86/Barcelona/dependency-breaking-sbb-1.s | 71 + .../X86/Barcelona/dependency-breaking-sbb-2.s | 78 + .../X86/Barcelona/int-to-fpu-forwarding-1.s | 194 ++ .../X86/Barcelona/int-to-fpu-forwarding-2.s | 182 ++ .../X86/Barcelona/int-to-fpu-forwarding-3.s | 74 + .../tools/llvm-mca/X86/Barcelona/one-idioms.s | 96 + .../X86/Barcelona/partial-reg-update-2.s | 47 + .../X86/Barcelona/partial-reg-update-3.s | 76 + .../X86/Barcelona/partial-reg-update-4.s | 77 + .../X86/Barcelona/partial-reg-update-5.s | 59 + .../X86/Barcelona/partial-reg-update-6.s | 79 + .../X86/Barcelona/partial-reg-update-7.s | 98 + .../X86/Barcelona/partial-reg-update.s | 47 + .../llvm-mca/X86/Barcelona/rcu-statistics.s | 64 + .../llvm-mca/X86/Barcelona/read-advance-1.s | 48 + .../llvm-mca/X86/Barcelona/read-advance-2.s | 47 + .../llvm-mca/X86/Barcelona/read-advance-3.s | 47 + .../X86/Barcelona/reg-move-elimination-1.s | 80 + .../X86/Barcelona/reg-move-elimination-2.s | 121 + .../X86/Barcelona/reg-move-elimination-3.s | 106 + .../X86/Barcelona/reg-move-elimination-4.s | 92 + .../X86/Barcelona/reg-move-elimination-5.s | 92 + .../X86/Barcelona/reg-move-elimination-6.s | 98 + .../llvm-mca/X86/Barcelona/resources-3dnow.s | 208 ++ .../llvm-mca/X86/Barcelona/resources-cmov.s | 323 +++ .../X86/Barcelona/resources-cmpxchg.s | 36 + .../llvm-mca/X86/Barcelona/resources-lea.s | 437 +++ .../llvm-mca/X86/Barcelona/resources-lzcnt.s | 50 + .../llvm-mca/X86/Barcelona/resources-mmx.s | 393 +++ .../llvm-mca/X86/Barcelona/resources-popcnt.s | 50 + .../X86/Barcelona/resources-prefetchw.s | 36 + .../llvm-mca/X86/Barcelona/resources-sse1.s | 461 +++ .../llvm-mca/X86/Barcelona/resources-sse2.s | 960 +++++++ .../llvm-mca/X86/Barcelona/resources-sse3.s | 104 + .../llvm-mca/X86/Barcelona/resources-sse4a.s | 50 + .../llvm-mca/X86/Barcelona/resources-x86_32.s | 78 + .../llvm-mca/X86/Barcelona/resources-x86_64.s | 2476 +++++++++++++++++ .../llvm-mca/X86/Barcelona/resources-x87.s | 521 ++++ .../llvm-mca/X86/Barcelona/zero-idioms.s | 242 ++ test/tools/llvm-mca/X86/cpus.s | 6 + test/tools/llvm-mca/X86/read-after-ld-1.s | 190 +- .../llvm-mca/X86/register-file-statistics.s | 71 +- .../llvm-mca/X86/scheduler-queue-usage.s | 10 + .../tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s | 25 + 48 files changed, 8928 insertions(+), 120 deletions(-) create mode 100644 test/tools/llvm-mca/X86/Barcelona/clear-super-register-1.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/dependency-breaking-cmp.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpeq.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpgt.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-1.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-2.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-1.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-2.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-3.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/one-idioms.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/partial-reg-update-2.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/partial-reg-update-3.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/partial-reg-update-4.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/partial-reg-update-5.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/partial-reg-update-6.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/partial-reg-update-7.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/partial-reg-update.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/rcu-statistics.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/read-advance-1.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/read-advance-2.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/read-advance-3.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-1.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-2.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-3.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-4.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-5.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-6.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-3dnow.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-cmov.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-cmpxchg.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-lea.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-lzcnt.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-mmx.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-popcnt.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-prefetchw.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-sse1.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-sse2.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-sse3.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-sse4a.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-x86_32.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/resources-x87.s create mode 100644 test/tools/llvm-mca/X86/Barcelona/zero-idioms.s diff --git a/test/tools/llvm-mca/X86/Barcelona/clear-super-register-1.s b/test/tools/llvm-mca/X86/Barcelona/clear-super-register-1.s new file mode 100644 index 00000000000..c8e18731a3e --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/clear-super-register-1.s @@ -0,0 +1,63 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=100 -resource-pressure=false -timeline -timeline-max-iterations=2 < %s | FileCheck %s + +## Sets register RAX. +imulq $5, %rcx, %rax + +## Kills the previous definition of RAX. +## The upper portion of RAX is cleared. +lzcnt %ecx, %eax + +## The AND can start immediately after the LZCNT. +## It doesn't need to wait for the IMUL. +and %rcx, %rax +bsf %rax, %rcx + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 803 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.50 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 imulq $5, %rcx, %rax +# CHECK-NEXT: 1 3 1.00 lzcntl %ecx, %eax +# CHECK-NEXT: 1 1 0.33 andq %rcx, %rax +# CHECK-NEXT: 1 3 1.00 bsfq %rax, %rcx + +# CHECK: Timeline view: +# CHECK-NEXT: 012345678 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER . . . imulq $5, %rcx, %rax +# CHECK-NEXT: [0,1] D=eeeER . . . lzcntl %ecx, %eax +# CHECK-NEXT: [0,2] D====eER . . . andq %rcx, %rax +# CHECK-NEXT: [0,3] D=====eeeER . . bsfq %rax, %rcx +# CHECK-NEXT: [1,0] .D=======eeeER . . imulq $5, %rcx, %rax +# CHECK-NEXT: [1,1] .D========eeeER. . lzcntl %ecx, %eax +# CHECK-NEXT: [1,2] .D===========eER . andq %rcx, %rax +# CHECK-NEXT: [1,3] .D============eeeER bsfq %rax, %rcx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 4.5 0.5 0.0 imulq $5, %rcx, %rax +# CHECK-NEXT: 1. 2 5.5 1.5 0.0 lzcntl %ecx, %eax +# CHECK-NEXT: 2. 2 8.5 0.0 0.0 andq %rcx, %rax +# CHECK-NEXT: 3. 2 9.5 0.0 0.0 bsfq %rax, %rcx diff --git a/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-cmp.s b/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-cmp.s new file mode 100644 index 00000000000..9c02249ba6b --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-cmp.s @@ -0,0 +1,70 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s + +# The CMP instruction doesn't depend on the value of EAX. It can set the flags +# without having to read the inputs. + +cmp %eax, %eax +cmovae %ebx, %eax + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 3000 +# CHECK-NEXT: Total Cycles: 4503 +# CHECK-NEXT: Total uOps: 4500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 0.67 +# CHECK-NEXT: Block RThroughput: 0.8 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 cmpl %eax, %eax +# CHECK-NEXT: 2 2 0.67 cmovael %ebx, %eax + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - 1.00 - - cmpl %eax, %eax +# CHECK-NEXT: - - 1.00 1.00 - - - - cmovael %ebx, %eax + +# CHECK: Timeline view: +# CHECK-NEXT: 01 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeER . .. cmpl %eax, %eax +# CHECK-NEXT: [0,1] D=eeER .. cmovael %ebx, %eax +# CHECK-NEXT: [1,0] D===eER .. cmpl %eax, %eax +# CHECK-NEXT: [1,1] .D===eeER .. cmovael %ebx, %eax +# CHECK-NEXT: [2,0] .D=====eER.. cmpl %eax, %eax +# CHECK-NEXT: [2,1] . D=====eeER cmovael %ebx, %eax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 3.7 0.3 0.0 cmpl %eax, %eax +# CHECK-NEXT: 1. 3 4.0 0.0 0.0 cmovael %ebx, %eax diff --git a/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpeq.s b/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpeq.s new file mode 100644 index 00000000000..6f10c76d77a --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpeq.s @@ -0,0 +1,107 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s + +# All of the vector packed compares from this test are dependency breaking +# instructions. That means, there is no RAW dependency between any of the +# instructions, and the code can be fully parallelized in hardware. + +pcmpeqb %mm0, %mm0 +pcmpeqd %mm0, %mm0 +pcmpeqw %mm0, %mm0 + +pcmpeqb %xmm0, %xmm0 +pcmpeqd %xmm0, %xmm0 +pcmpeqq %xmm0, %xmm0 +pcmpeqw %xmm0, %xmm0 + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 10500 +# CHECK-NEXT: Total Cycles: 13503 +# CHECK-NEXT: Total uOps: 10500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.78 +# CHECK-NEXT: IPC: 0.78 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 pcmpeqb %mm0, %mm0 +# CHECK-NEXT: 1 3 1.00 pcmpeqd %mm0, %mm0 +# CHECK-NEXT: 1 3 1.00 pcmpeqw %mm0, %mm0 +# CHECK-NEXT: 1 1 0.50 pcmpeqb %xmm0, %xmm0 +# CHECK-NEXT: 1 1 0.50 pcmpeqd %xmm0, %xmm0 +# CHECK-NEXT: 1 1 0.50 pcmpeqq %xmm0, %xmm0 +# CHECK-NEXT: 1 1 0.50 pcmpeqw %xmm0, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 4.01 - 2.99 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqb %mm0, %mm0 +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqd %mm0, %mm0 +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqw %mm0, %mm0 +# CHECK-NEXT: - - - 0.01 - 0.99 - - pcmpeqb %xmm0, %xmm0 +# CHECK-NEXT: - - - 0.01 - 0.99 - - pcmpeqd %xmm0, %xmm0 +# CHECK-NEXT: - - - 0.01 - 0.99 - - pcmpeqq %xmm0, %xmm0 +# CHECK-NEXT: - - - 0.99 - 0.01 - - pcmpeqw %xmm0, %xmm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeER . . . . . pcmpeqb %mm0, %mm0 +# CHECK-NEXT: [0,1] D===eeeER . . . . . pcmpeqd %mm0, %mm0 +# CHECK-NEXT: [0,2] D======eeeER . . . . pcmpeqw %mm0, %mm0 +# CHECK-NEXT: [0,3] DeE--------R . . . . pcmpeqb %xmm0, %xmm0 +# CHECK-NEXT: [0,4] .DeE-------R . . . . pcmpeqd %xmm0, %xmm0 +# CHECK-NEXT: [0,5] .D=eE------R . . . . pcmpeqq %xmm0, %xmm0 +# CHECK-NEXT: [0,6] .D==eE-----R . . . . pcmpeqw %xmm0, %xmm0 +# CHECK-NEXT: [1,0] .D========eeeER. . . . pcmpeqb %mm0, %mm0 +# CHECK-NEXT: [1,1] . D==========eeeER . . . pcmpeqd %mm0, %mm0 +# CHECK-NEXT: [1,2] . D=============eeeER . . pcmpeqw %mm0, %mm0 +# CHECK-NEXT: [1,3] . D==eE-------------R . . pcmpeqb %xmm0, %xmm0 +# CHECK-NEXT: [1,4] . D===eE------------R . . pcmpeqd %xmm0, %xmm0 +# CHECK-NEXT: [1,5] . D===eE-----------R . . pcmpeqq %xmm0, %xmm0 +# CHECK-NEXT: [1,6] . D====eE----------R . . pcmpeqw %xmm0, %xmm0 +# CHECK-NEXT: [2,0] . D===============eeeER . . pcmpeqb %mm0, %mm0 +# CHECK-NEXT: [2,1] . D==================eeeER . pcmpeqd %mm0, %mm0 +# CHECK-NEXT: [2,2] . D====================eeeER pcmpeqw %mm0, %mm0 +# CHECK-NEXT: [2,3] . D====eE------------------R pcmpeqb %xmm0, %xmm0 +# CHECK-NEXT: [2,4] . D=====eE-----------------R pcmpeqd %xmm0, %xmm0 +# CHECK-NEXT: [2,5] . D======eE----------------R pcmpeqq %xmm0, %xmm0 +# CHECK-NEXT: [2,6] . D======eE---------------R pcmpeqw %xmm0, %xmm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 8.7 0.3 0.0 pcmpeqb %mm0, %mm0 +# CHECK-NEXT: 1. 3 11.3 0.0 0.0 pcmpeqd %mm0, %mm0 +# CHECK-NEXT: 2. 3 14.0 0.0 0.0 pcmpeqw %mm0, %mm0 +# CHECK-NEXT: 3. 3 3.0 0.3 13.0 pcmpeqb %xmm0, %xmm0 +# CHECK-NEXT: 4. 3 3.7 0.0 12.0 pcmpeqd %xmm0, %xmm0 +# CHECK-NEXT: 5. 3 4.3 0.0 11.0 pcmpeqq %xmm0, %xmm0 +# CHECK-NEXT: 6. 3 5.0 0.0 10.0 pcmpeqw %xmm0, %xmm0 diff --git a/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpgt.s b/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpgt.s new file mode 100644 index 00000000000..ceb8c52e3ad --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpgt.s @@ -0,0 +1,108 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s + +# All of the vector packed compares from this test are zero idioms. These zero +# idioms are all detected and removed by the register renamer. That means, no +# uOp is executed, and there is no RAW dependency for any of the packed +# compares. + +pcmpgtb %mm0, %mm0 +pcmpgtd %mm0, %mm0 +pcmpgtw %mm0, %mm0 + +pcmpgtb %xmm0, %xmm0 +pcmpgtd %xmm0, %xmm0 +pcmpgtq %xmm0, %xmm0 +pcmpgtw %xmm0, %xmm0 + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 10500 +# CHECK-NEXT: Total Cycles: 13503 +# CHECK-NEXT: Total uOps: 10500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.78 +# CHECK-NEXT: IPC: 0.78 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 pcmpgtb %mm0, %mm0 +# CHECK-NEXT: 1 3 1.00 pcmpgtd %mm0, %mm0 +# CHECK-NEXT: 1 3 1.00 pcmpgtw %mm0, %mm0 +# CHECK-NEXT: 1 0 0.25 pcmpgtb %xmm0, %xmm0 +# CHECK-NEXT: 1 0 0.25 pcmpgtd %xmm0, %xmm0 +# CHECK-NEXT: 1 0 0.25 pcmpgtq %xmm0, %xmm0 +# CHECK-NEXT: 1 0 0.25 pcmpgtw %xmm0, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 3.00 - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtb %mm0, %mm0 +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtd %mm0, %mm0 +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtw %mm0, %mm0 +# CHECK-NEXT: - - - - - - - - pcmpgtb %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - - pcmpgtd %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - - pcmpgtq %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - - pcmpgtw %xmm0, %xmm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeER . . . . . pcmpgtb %mm0, %mm0 +# CHECK-NEXT: [0,1] D===eeeER . . . . . pcmpgtd %mm0, %mm0 +# CHECK-NEXT: [0,2] D======eeeER . . . . pcmpgtw %mm0, %mm0 +# CHECK-NEXT: [0,3] D----------R . . . . pcmpgtb %xmm0, %xmm0 +# CHECK-NEXT: [0,4] .D---------R . . . . pcmpgtd %xmm0, %xmm0 +# CHECK-NEXT: [0,5] .D---------R . . . . pcmpgtq %xmm0, %xmm0 +# CHECK-NEXT: [0,6] .D---------R . . . . pcmpgtw %xmm0, %xmm0 +# CHECK-NEXT: [1,0] .D========eeeER. . . . pcmpgtb %mm0, %mm0 +# CHECK-NEXT: [1,1] . D==========eeeER . . . pcmpgtd %mm0, %mm0 +# CHECK-NEXT: [1,2] . D=============eeeER . . pcmpgtw %mm0, %mm0 +# CHECK-NEXT: [1,3] . D-----------------R . . pcmpgtb %xmm0, %xmm0 +# CHECK-NEXT: [1,4] . D-----------------R . . pcmpgtd %xmm0, %xmm0 +# CHECK-NEXT: [1,5] . D----------------R . . pcmpgtq %xmm0, %xmm0 +# CHECK-NEXT: [1,6] . D----------------R . . pcmpgtw %xmm0, %xmm0 +# CHECK-NEXT: [2,0] . D===============eeeER . . pcmpgtb %mm0, %mm0 +# CHECK-NEXT: [2,1] . D==================eeeER . pcmpgtd %mm0, %mm0 +# CHECK-NEXT: [2,2] . D====================eeeER pcmpgtw %mm0, %mm0 +# CHECK-NEXT: [2,3] . D------------------------R pcmpgtb %xmm0, %xmm0 +# CHECK-NEXT: [2,4] . D------------------------R pcmpgtd %xmm0, %xmm0 +# CHECK-NEXT: [2,5] . D------------------------R pcmpgtq %xmm0, %xmm0 +# CHECK-NEXT: [2,6] . D-----------------------R pcmpgtw %xmm0, %xmm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 8.7 0.3 0.0 pcmpgtb %mm0, %mm0 +# CHECK-NEXT: 1. 3 11.3 0.0 0.0 pcmpgtd %mm0, %mm0 +# CHECK-NEXT: 2. 3 14.0 0.0 0.0 pcmpgtw %mm0, %mm0 +# CHECK-NEXT: 3. 3 0.0 0.0 17.0 pcmpgtb %xmm0, %xmm0 +# CHECK-NEXT: 4. 3 0.0 0.0 16.7 pcmpgtd %xmm0, %xmm0 +# CHECK-NEXT: 5. 3 0.0 0.0 16.3 pcmpgtq %xmm0, %xmm0 +# CHECK-NEXT: 6. 3 0.0 0.0 16.0 pcmpgtw %xmm0, %xmm0 diff --git a/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-1.s b/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-1.s new file mode 100644 index 00000000000..38aeb813b11 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-1.s @@ -0,0 +1,71 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s + +# Although both SBB are dependency breaking instructions, there is still an +# implicit dependency on EFLAGS which limits the ILP. So, the hardware backend +# can only execute one instruction per cycle. + +sbb %edx, %edx +sbb %eax, %eax + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 3000 +# CHECK-NEXT: Total Cycles: 6003 +# CHECK-NEXT: Total uOps: 6000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 2 0.67 sbbl %edx, %edx +# CHECK-NEXT: 2 2 0.67 sbbl %eax, %eax + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.33 1.33 - 1.33 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - sbbl %edx, %edx +# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - sbbl %eax, %eax + +# CHECK: Timeline view: +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeER. . . sbbl %edx, %edx +# CHECK-NEXT: [0,1] D==eeER . . sbbl %eax, %eax +# CHECK-NEXT: [1,0] .D===eeER . . sbbl %edx, %edx +# CHECK-NEXT: [1,1] .D=====eeER . sbbl %eax, %eax +# CHECK-NEXT: [2,0] . D======eeER . sbbl %edx, %edx +# CHECK-NEXT: [2,1] . D========eeER sbbl %eax, %eax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 4.0 0.3 0.0 sbbl %edx, %edx +# CHECK-NEXT: 1. 3 6.0 0.0 0.0 sbbl %eax, %eax diff --git a/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-2.s b/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-2.s new file mode 100644 index 00000000000..bae6f563421 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-2.s @@ -0,0 +1,78 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s + +# The SBB does not depend on the value of register EAX. That means, it doesn't +# have to wait for the IMUL to write-back on EAX. However, it still depends on +# the ADD for EFLAGS. + +imul %edx, %eax +add %edx, %edx +sbb %eax, %eax + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 4500 +# CHECK-NEXT: Total Cycles: 7503 +# CHECK-NEXT: Total uOps: 6000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.80 +# CHECK-NEXT: IPC: 0.60 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 imull %edx, %eax +# CHECK-NEXT: 1 1 0.33 addl %edx, %edx +# CHECK-NEXT: 2 2 0.67 sbbl %eax, %eax + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.33 1.33 - 1.33 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - imull %edx, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.34 - - addl %edx, %edx +# CHECK-NEXT: - - 1.00 - - 1.00 - - sbbl %eax, %eax + +# CHECK: Timeline view: +# CHECK-NEXT: 01234567 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER . . . imull %edx, %eax +# CHECK-NEXT: [0,1] DeE--R . . . addl %edx, %edx +# CHECK-NEXT: [0,2] D===eeER . . . sbbl %eax, %eax +# CHECK-NEXT: [1,0] .D====eeeER . . imull %edx, %eax +# CHECK-NEXT: [1,1] .DeE------R . . addl %edx, %edx +# CHECK-NEXT: [1,2] .D=======eeER . . sbbl %eax, %eax +# CHECK-NEXT: [2,0] . D========eeeER . imull %edx, %eax +# CHECK-NEXT: [2,1] . DeE----------R . addl %edx, %edx +# CHECK-NEXT: [2,2] . D===========eeER sbbl %eax, %eax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 5.0 0.3 0.0 imull %edx, %eax +# CHECK-NEXT: 1. 3 1.0 0.3 6.0 addl %edx, %edx +# CHECK-NEXT: 2. 3 8.0 0.0 0.0 sbbl %eax, %eax diff --git a/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-1.s b/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-1.s new file mode 100644 index 00000000000..874dfab2a6d --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-1.s @@ -0,0 +1,194 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=500 < %s | FileCheck %s + +# LLVM-MCA-BEGIN +pinsrb $0, %eax, %xmm0 +pinsrb $1, %eax, %xmm0 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN +pinsrw $0, %eax, %xmm0 +pinsrw $1, %eax, %xmm0 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN +pinsrd $0, %eax, %xmm0 +pinsrd $1, %eax, %xmm0 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN +pinsrq $0, %rax, %xmm0 +pinsrq $1, %rax, %xmm0 +# LLVM-MCA-END + +# CHECK: [0] Code Region + +# CHECK: Iterations: 500 +# CHECK-NEXT: Instructions: 1000 +# CHECK-NEXT: Total Cycles: 2003 +# CHECK-NEXT: Total uOps: 2000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 2 1.00 pinsrb $0, %eax, %xmm0 +# CHECK-NEXT: 2 2 1.00 pinsrb $1, %eax, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 2.00 - 2.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrb $0, %eax, %xmm0 +# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrb $1, %eax, %xmm0 + +# CHECK: [1] Code Region + +# CHECK: Iterations: 500 +# CHECK-NEXT: Instructions: 1000 +# CHECK-NEXT: Total Cycles: 2003 +# CHECK-NEXT: Total uOps: 2000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 2 1.00 pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: 2 2 1.00 pinsrw $1, %eax, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 2.00 - 2.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrw $1, %eax, %xmm0 + +# CHECK: [2] Code Region + +# CHECK: Iterations: 500 +# CHECK-NEXT: Instructions: 1000 +# CHECK-NEXT: Total Cycles: 2003 +# CHECK-NEXT: Total uOps: 2000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 2 1.00 pinsrd $0, %eax, %xmm0 +# CHECK-NEXT: 2 2 1.00 pinsrd $1, %eax, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 2.00 - 2.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrd $0, %eax, %xmm0 +# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrd $1, %eax, %xmm0 + +# CHECK: [3] Code Region + +# CHECK: Iterations: 500 +# CHECK-NEXT: Instructions: 1000 +# CHECK-NEXT: Total Cycles: 2003 +# CHECK-NEXT: Total uOps: 2000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 2 1.00 pinsrq $0, %rax, %xmm0 +# CHECK-NEXT: 2 2 1.00 pinsrq $1, %rax, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 2.00 - 2.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrq $0, %rax, %xmm0 +# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrq $1, %rax, %xmm0 diff --git a/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-2.s b/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-2.s new file mode 100644 index 00000000000..c5b1019a6dd --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-2.s @@ -0,0 +1,182 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=500 < %s | FileCheck %s + +# LLVM-MCA-BEGIN +cvtsi2ss %ecx, %xmm0 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN +cvtsi2sd %ecx, %xmm0 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN +movd %ecx, %xmm0 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN +movq %rcx, %xmm0 +# LLVM-MCA-END + +# CHECK: [0] Code Region + +# CHECK: Iterations: 500 +# CHECK-NEXT: Instructions: 500 +# CHECK-NEXT: Total Cycles: 2503 +# CHECK-NEXT: Total uOps: 1500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.60 +# CHECK-NEXT: IPC: 0.20 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 3 5 2.00 cvtsi2ss %ecx, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 1.00 - 2.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - 2.00 - - cvtsi2ss %ecx, %xmm0 + +# CHECK: [1] Code Region + +# CHECK: Iterations: 500 +# CHECK-NEXT: Instructions: 500 +# CHECK-NEXT: Total Cycles: 2003 +# CHECK-NEXT: Total uOps: 1000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.50 +# CHECK-NEXT: IPC: 0.25 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 4 1.00 cvtsi2sd %ecx, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtsi2sd %ecx, %xmm0 + +# CHECK: [2] Code Region + +# CHECK: Iterations: 500 +# CHECK-NEXT: Instructions: 500 +# CHECK-NEXT: Total Cycles: 503 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.99 +# CHECK-NEXT: IPC: 0.99 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 1.00 movd %ecx, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - - - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - 1.00 - - movd %ecx, %xmm0 + +# CHECK: [3] Code Region + +# CHECK: Iterations: 500 +# CHECK-NEXT: Instructions: 500 +# CHECK-NEXT: Total Cycles: 503 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.99 +# CHECK-NEXT: IPC: 0.99 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 1.00 movq %rcx, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - - - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - 1.00 - - movq %rcx, %xmm0 diff --git a/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-3.s b/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-3.s new file mode 100644 index 00000000000..5cf5ca1cc87 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-3.s @@ -0,0 +1,74 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +add %eax, %eax +pinsrw $0, %eax, %xmm0 +pinsrw $1, %eax, %xmm0 + +# CHECK: Iterations: 500 +# CHECK-NEXT: Instructions: 1500 +# CHECK-NEXT: Total Cycles: 2004 +# CHECK-NEXT: Total uOps: 2500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.25 +# CHECK-NEXT: IPC: 0.75 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 addl %eax, %eax +# CHECK-NEXT: 2 2 1.00 pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: 2 2 1.00 pinsrw $1, %eax, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 0.98 2.01 - 2.01 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.98 0.01 - 0.01 - - addl %eax, %eax +# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrw $1, %eax, %xmm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 012345 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeER . . . addl %eax, %eax +# CHECK-NEXT: [0,1] D=eeER . . pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: [0,2] .D==eeER . . pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: [1,0] .DeE---R . . addl %eax, %eax +# CHECK-NEXT: [1,1] . D===eeER. . pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: [1,2] . D=====eeER . pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: [2,0] . DeE-----R . addl %eax, %eax +# CHECK-NEXT: [2,1] . D======eeER . pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: [2,2] . D=======eeER pinsrw $1, %eax, %xmm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 1.0 0.7 2.7 addl %eax, %eax +# CHECK-NEXT: 1. 3 4.3 0.0 0.0 pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: 2. 3 5.7 0.0 0.0 pinsrw $1, %eax, %xmm0 diff --git a/test/tools/llvm-mca/X86/Barcelona/one-idioms.s b/test/tools/llvm-mca/X86/Barcelona/one-idioms.s new file mode 100644 index 00000000000..5fc423132fa --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/one-idioms.s @@ -0,0 +1,96 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=1 -register-file-stats < %s | FileCheck %s + +# These are dependency-breaking one-idioms. +# Much like zero-idioms, but they produce ones, and do consume resources. + +pcmpeqb %mm2, %mm2 +pcmpeqd %mm2, %mm2 +pcmpeqw %mm2, %mm2 + +pcmpeqb %xmm2, %xmm2 +pcmpeqd %xmm2, %xmm2 +pcmpeqq %xmm2, %xmm2 +pcmpeqw %xmm2, %xmm2 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 700 +# CHECK-NEXT: Total Cycles: 903 +# CHECK-NEXT: Total uOps: 700 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.78 +# CHECK-NEXT: IPC: 0.78 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 pcmpeqb %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpeqd %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpeqw %mm2, %mm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqw %xmm2, %xmm2 + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 700 +# CHECK-NEXT: Max number of mappings used: 128 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 4.10 - 2.90 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqb %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqd %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqw %mm2, %mm2 +# CHECK-NEXT: - - - 0.10 - 0.90 - - pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: - - - 0.10 - 0.90 - - pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: - - - 0.11 - 0.89 - - pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: - - - 0.79 - 0.21 - - pcmpeqw %xmm2, %xmm2 + +# CHECK: Timeline view: +# CHECK-NEXT: 01 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER .. pcmpeqb %mm2, %mm2 +# CHECK-NEXT: [0,1] D===eeeER .. pcmpeqd %mm2, %mm2 +# CHECK-NEXT: [0,2] D======eeeER pcmpeqw %mm2, %mm2 +# CHECK-NEXT: [0,3] DeE--------R pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: [0,4] .DeE-------R pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: [0,5] .D=eE------R pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: [0,6] .D==eE-----R pcmpeqw %xmm2, %xmm2 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 pcmpeqb %mm2, %mm2 +# CHECK-NEXT: 1. 1 4.0 0.0 0.0 pcmpeqd %mm2, %mm2 +# CHECK-NEXT: 2. 1 7.0 0.0 0.0 pcmpeqw %mm2, %mm2 +# CHECK-NEXT: 3. 1 1.0 1.0 8.0 pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: 4. 1 1.0 0.0 7.0 pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: 5. 1 2.0 0.0 6.0 pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: 6. 1 3.0 0.0 5.0 pcmpeqw %xmm2, %xmm2 diff --git a/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-2.s b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-2.s new file mode 100644 index 00000000000..91ecc93c880 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-2.s @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s + +imul %rax, %rbx +lzcnt %ax, %bx +add %ecx, %ebx + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 3 +# CHECK-NEXT: Total Cycles: 8 +# CHECK-NEXT: Total uOps: 3 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.38 +# CHECK-NEXT: IPC: 0.38 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 imulq %rax, %rbx +# CHECK-NEXT: 1 3 1.00 lzcntw %ax, %bx +# CHECK-NEXT: 1 1 0.33 addl %ecx, %ebx + +# CHECK: Timeline view: +# CHECK-NEXT: Index 01234567 + +# CHECK: [0,0] DeeeER . imulq %rax, %rbx +# CHECK-NEXT: [0,1] D=eeeER. lzcntw %ax, %bx +# CHECK-NEXT: [0,2] D====eER addl %ecx, %ebx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rbx +# CHECK-NEXT: 1. 1 2.0 2.0 0.0 lzcntw %ax, %bx +# CHECK-NEXT: 2. 1 5.0 0.0 0.0 addl %ecx, %ebx diff --git a/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-3.s b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-3.s new file mode 100644 index 00000000000..32e143e920d --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-3.s @@ -0,0 +1,76 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +# The ILP is limited by the false dependency on %dx. So, the mov cannot execute +# in parallel with the add. + +add %cx, %dx +mov %ax, %dx +xor %bx, %dx + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 4500 +# CHECK-NEXT: Total Cycles: 1504 +# CHECK-NEXT: Total uOps: 4500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 2.99 +# CHECK-NEXT: IPC: 2.99 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 addw %cx, %dx +# CHECK-NEXT: 1 1 0.33 movw %ax, %dx +# CHECK-NEXT: 1 1 0.33 xorw %bx, %dx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.67 - - 0.33 - - addw %cx, %dx +# CHECK-NEXT: - - - 0.67 - 0.33 - - movw %ax, %dx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw %bx, %dx + +# CHECK: Timeline view: +# CHECK-NEXT: Index 0123456 + +# CHECK: [0,0] DeER .. addw %cx, %dx +# CHECK-NEXT: [0,1] DeER .. movw %ax, %dx +# CHECK-NEXT: [0,2] D=eER.. xorw %bx, %dx +# CHECK-NEXT: [1,0] D==eER. addw %cx, %dx +# CHECK-NEXT: [1,1] .DeE-R. movw %ax, %dx +# CHECK-NEXT: [1,2] .D=eER. xorw %bx, %dx +# CHECK-NEXT: [2,0] .D==eER addw %cx, %dx +# CHECK-NEXT: [2,1] .DeE--R movw %ax, %dx +# CHECK-NEXT: [2,2] . DeE-R xorw %bx, %dx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 2.3 0.3 0.0 addw %cx, %dx +# CHECK-NEXT: 1. 3 1.0 1.0 1.0 movw %ax, %dx +# CHECK-NEXT: 2. 3 1.7 0.0 0.3 xorw %bx, %dx diff --git a/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-4.s b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-4.s new file mode 100644 index 00000000000..3a9bd92d023 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-4.s @@ -0,0 +1,77 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +# The lzcnt cannot execute in parallel with the imul because there is a false +# dependency on %bx. + +imul %ax, %bx +lzcnt %ax, %bx +add %cx, %bx + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 4500 +# CHECK-NEXT: Total Cycles: 3005 +# CHECK-NEXT: Total uOps: 4500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.50 +# CHECK-NEXT: IPC: 1.50 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 imulw %ax, %bx +# CHECK-NEXT: 1 3 1.00 lzcntw %ax, %bx +# CHECK-NEXT: 1 1 0.33 addw %cx, %bx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 0.50 2.00 - 0.50 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - imulw %ax, %bx +# CHECK-NEXT: - - - 1.00 - - - - lzcntw %ax, %bx +# CHECK-NEXT: - - 0.50 - - 0.50 - - addw %cx, %bx + +# CHECK: Timeline view: +# CHECK-NEXT: 01 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER .. imulw %ax, %bx +# CHECK-NEXT: [0,1] D=eeeER .. lzcntw %ax, %bx +# CHECK-NEXT: [0,2] D====eER .. addw %cx, %bx +# CHECK-NEXT: [1,0] D=====eeeER. imulw %ax, %bx +# CHECK-NEXT: [1,1] .D=eeeE---R. lzcntw %ax, %bx +# CHECK-NEXT: [1,2] .D====eE--R. addw %cx, %bx +# CHECK-NEXT: [2,0] .D=====eeeER imulw %ax, %bx +# CHECK-NEXT: [2,1] .D==eeeE---R lzcntw %ax, %bx +# CHECK-NEXT: [2,2] . D====eE--R addw %cx, %bx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 4.3 0.3 0.0 imulw %ax, %bx +# CHECK-NEXT: 1. 3 2.3 2.3 2.0 lzcntw %ax, %bx +# CHECK-NEXT: 2. 3 5.0 0.0 1.3 addw %cx, %bx diff --git a/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-5.s b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-5.s new file mode 100644 index 00000000000..fcda6302947 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-5.s @@ -0,0 +1,59 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +lzcnt %ax, %bx ## partial register stall. + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 1500 +# CHECK-NEXT: Total Cycles: 1505 +# CHECK-NEXT: Total uOps: 1500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 lzcntw %ax, %bx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 1.00 - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - lzcntw %ax, %bx + +# CHECK: Timeline view: +# CHECK-NEXT: Index 01234567 + +# CHECK: [0,0] DeeeER . lzcntw %ax, %bx +# CHECK-NEXT: [1,0] D=eeeER. lzcntw %ax, %bx +# CHECK-NEXT: [2,0] D==eeeER lzcntw %ax, %bx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 2.0 2.0 0.0 lzcntw %ax, %bx diff --git a/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-6.s b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-6.s new file mode 100644 index 00000000000..18d1f5a215e --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-6.s @@ -0,0 +1,79 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +# Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the +# imul. However, the folded load can start immediately. +# The last lzcnt has a false dependency on %cx. However, even in this case, the +# folded load can start immediately. + +imul %edx, %ecx +lzcnt (%rsp), %cx +lzcnt 2(%rsp), %cx + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 4500 +# CHECK-NEXT: Total Cycles: 4510 +# CHECK-NEXT: Total uOps: 7500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.66 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 imull %edx, %ecx +# CHECK-NEXT: 2 8 1.00 * lzcntw (%rsp), %cx +# CHECK-NEXT: 2 8 1.00 * lzcntw 2(%rsp), %cx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 3.00 - - 1.00 1.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - imull %edx, %ecx +# CHECK-NEXT: - - - 1.00 - - - 1.00 lzcntw (%rsp), %cx +# CHECK-NEXT: - - - 1.00 - - 1.00 - lzcntw 2(%rsp), %cx + +# CHECK: Timeline view: +# CHECK-NEXT: 012345678 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER . . . imull %edx, %ecx +# CHECK-NEXT: [0,1] D=eeeeeeeeER . . lzcntw (%rsp), %cx +# CHECK-NEXT: [0,2] .D=eeeeeeeeER . . lzcntw 2(%rsp), %cx +# CHECK-NEXT: [1,0] .D=========eeeER . imull %edx, %ecx +# CHECK-NEXT: [1,1] . D=eeeeeeeeE--R . lzcntw (%rsp), %cx +# CHECK-NEXT: [1,2] . D==eeeeeeeeE-R . lzcntw 2(%rsp), %cx +# CHECK-NEXT: [2,0] . D==========eeeER imull %edx, %ecx +# CHECK-NEXT: [2,1] . D==eeeeeeeeE---R lzcntw (%rsp), %cx +# CHECK-NEXT: [2,2] . D==eeeeeeeeE--R lzcntw 2(%rsp), %cx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 7.3 0.3 0.0 imull %edx, %ecx +# CHECK-NEXT: 1. 3 2.3 2.3 1.7 lzcntw (%rsp), %cx +# CHECK-NEXT: 2. 3 2.7 2.7 1.0 lzcntw 2(%rsp), %cx diff --git a/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-7.s b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-7.s new file mode 100644 index 00000000000..b7634f890cd --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-7.s @@ -0,0 +1,98 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=5 < %s | FileCheck %s + +sete %r9b +movzbl %al, %eax +shll $2, %eax +imull %ecx, %eax +cmpl $1025, %eax + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 500 +# CHECK-NEXT: Total Cycles: 504 +# CHECK-NEXT: Total uOps: 500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.99 +# CHECK-NEXT: IPC: 0.99 +# CHECK-NEXT: Block RThroughput: 1.3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.50 sete %r9b +# CHECK-NEXT: 1 1 0.33 movzbl %al, %eax +# CHECK-NEXT: 1 1 0.50 shll $2, %eax +# CHECK-NEXT: 1 3 1.00 imull %ecx, %eax +# CHECK-NEXT: 1 1 0.33 cmpl $1025, %eax + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.66 1.67 - 1.67 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.66 - - 0.34 - - sete %r9b +# CHECK-NEXT: - - 0.33 0.34 - 0.33 - - movzbl %al, %eax +# CHECK-NEXT: - - 0.34 - - 0.66 - - shll $2, %eax +# CHECK-NEXT: - - - 1.00 - - - - imull %ecx, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.34 - - cmpl $1025, %eax + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012345678 + +# CHECK: [0,0] DeER . . . . . . sete %r9b +# CHECK-NEXT: [0,1] DeER . . . . . . movzbl %al, %eax +# CHECK-NEXT: [0,2] D=eER. . . . . . shll $2, %eax +# CHECK-NEXT: [0,3] D==eeeER . . . . . imull %ecx, %eax +# CHECK-NEXT: [0,4] .D====eER . . . . . cmpl $1025, %eax +# CHECK-NEXT: [1,0] .D=====eER. . . . . sete %r9b +# CHECK-NEXT: [1,1] .D====eE-R. . . . . movzbl %al, %eax +# CHECK-NEXT: [1,2] .D=====eER. . . . . shll $2, %eax +# CHECK-NEXT: [1,3] . D=====eeeER . . . . imull %ecx, %eax +# CHECK-NEXT: [1,4] . D========eER . . . . cmpl $1025, %eax +# CHECK-NEXT: [2,0] . D=========eER. . . . sete %r9b +# CHECK-NEXT: [2,1] . D========eE-R. . . . movzbl %al, %eax +# CHECK-NEXT: [2,2] . D========eER. . . . shll $2, %eax +# CHECK-NEXT: [2,3] . D=========eeeER . . . imull %ecx, %eax +# CHECK-NEXT: [2,4] . D============eER . . . cmpl $1025, %eax +# CHECK-NEXT: [3,0] . D=============eER. . . sete %r9b +# CHECK-NEXT: [3,1] . D===========eE-R. . . movzbl %al, %eax +# CHECK-NEXT: [3,2] . D============eER. . . shll $2, %eax +# CHECK-NEXT: [3,3] . D=============eeeER . . imull %ecx, %eax +# CHECK-NEXT: [3,4] . D================eER . . cmpl $1025, %eax +# CHECK-NEXT: [4,0] . D================eER. . sete %r9b +# CHECK-NEXT: [4,1] . D===============eE-R. . movzbl %al, %eax +# CHECK-NEXT: [4,2] . D================eER. . shll $2, %eax +# CHECK-NEXT: [4,3] . D=================eeeER. imull %ecx, %eax +# CHECK-NEXT: [4,4] . .D===================eER cmpl $1025, %eax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 5 9.6 0.2 0.0 sete %r9b +# CHECK-NEXT: 1. 5 8.6 0.2 0.8 movzbl %al, %eax +# CHECK-NEXT: 2. 5 9.4 0.0 0.0 shll $2, %eax +# CHECK-NEXT: 3. 5 10.2 0.0 0.0 imull %ecx, %eax +# CHECK-NEXT: 4. 5 12.8 0.0 0.0 cmpl $1025, %eax diff --git a/test/tools/llvm-mca/X86/Barcelona/partial-reg-update.s b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update.s new file mode 100644 index 00000000000..995bb35d3ac --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/partial-reg-update.s @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s + +imul %ax, %cx +add %al, %cl +add %ecx, %ebx + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 3 +# CHECK-NEXT: Total Cycles: 8 +# CHECK-NEXT: Total uOps: 3 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.38 +# CHECK-NEXT: IPC: 0.38 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 imulw %ax, %cx +# CHECK-NEXT: 1 1 0.33 addb %al, %cl +# CHECK-NEXT: 1 1 0.33 addl %ecx, %ebx + +# CHECK: Timeline view: +# CHECK-NEXT: Index 01234567 + +# CHECK: [0,0] DeeeER . imulw %ax, %cx +# CHECK-NEXT: [0,1] D===eER. addb %al, %cl +# CHECK-NEXT: [0,2] D====eER addl %ecx, %ebx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulw %ax, %cx +# CHECK-NEXT: 1. 1 4.0 0.0 0.0 addb %al, %cl +# CHECK-NEXT: 2. 1 5.0 0.0 0.0 addl %ecx, %ebx diff --git a/test/tools/llvm-mca/X86/Barcelona/rcu-statistics.s b/test/tools/llvm-mca/X86/Barcelona/rcu-statistics.s new file mode 100644 index 00000000000..50c45bc4dea --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/rcu-statistics.s @@ -0,0 +1,64 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -resource-pressure=false -retire-stats -iterations=1 < %s | FileCheck %s + +sqrtps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 +addps %xmm0, %xmm1 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 16 +# CHECK-NEXT: Total Cycles: 62 +# CHECK-NEXT: Total uOps: 16 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.26 +# CHECK-NEXT: IPC: 0.26 +# CHECK-NEXT: Block RThroughput: 15.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 14 14.00 sqrtps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 + +# CHECK: Retire Control Unit - number of cycles where we saw N instructions retired: +# CHECK-NEXT: [# retired], [# cycles] +# CHECK-NEXT: 0, 46 (74.2%) +# CHECK-NEXT: 1, 16 (25.8%) + +# CHECK: Total ROB Entries: 168 +# CHECK-NEXT: Max Used ROB Entries: 16 ( 9.5% ) +# CHECK-NEXT: Average Used ROB Entries per cy: 9 ( 5.4% ) diff --git a/test/tools/llvm-mca/X86/Barcelona/read-advance-1.s b/test/tools/llvm-mca/X86/Barcelona/read-advance-1.s new file mode 100644 index 00000000000..df66a44224a --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/read-advance-1.s @@ -0,0 +1,48 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s + +# The vmul can start executing 2cy in advance. That is beause the first use +# operand (i.e. %xmm1) is a ReadAfterLd. That means, the memory operand is +# evaluated before %xmm1. + +addps %xmm0, %xmm1 +mulps (%rdi), %xmm1 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 14 +# CHECK-NEXT: Total uOps: 3 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.21 +# CHECK-NEXT: IPC: 0.14 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 2 11 1.00 * mulps (%rdi), %xmm1 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER . . addps %xmm0, %xmm1 +# CHECK-NEXT: [0,1] DeeeeeeeeeeeER mulps (%rdi), %xmm1 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 addps %xmm0, %xmm1 +# CHECK-NEXT: 1. 1 1.0 0.0 0.0 mulps (%rdi), %xmm1 diff --git a/test/tools/llvm-mca/X86/Barcelona/read-advance-2.s b/test/tools/llvm-mca/X86/Barcelona/read-advance-2.s new file mode 100644 index 00000000000..6f04df6e13b --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/read-advance-2.s @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=0 -timeline < %s | FileCheck %s + +imull %esi +imull (%rdi) + +# The second integer multiply can start at cycle 2 because the implicit reads +# can start after the load operand is evaluated. + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 13 +# CHECK-NEXT: Total uOps: 7 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.54 +# CHECK-NEXT: IPC: 0.15 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 3 4 1.00 imull %esi +# CHECK-NEXT: 4 9 1.00 * imull (%rdi) + +# CHECK: Timeline view: +# CHECK-NEXT: 012 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeeER . . imull %esi +# CHECK-NEXT: [0,1] .DeeeeeeeeeER imull (%rdi) + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imull %esi +# CHECK-NEXT: 1. 1 1.0 1.0 0.0 imull (%rdi) diff --git a/test/tools/llvm-mca/X86/Barcelona/read-advance-3.s b/test/tools/llvm-mca/X86/Barcelona/read-advance-3.s new file mode 100644 index 00000000000..1b39f8bcdd6 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/read-advance-3.s @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=0 -timeline -dispatch=3 < %s | FileCheck %s + +add %rdi, %rsi +add (%rsp), %rsi +add %rdx, %r8 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 3 +# CHECK-NEXT: Total Cycles: 9 +# CHECK-NEXT: Total uOps: 4 + +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.44 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 1.3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 addq %rdi, %rsi +# CHECK-NEXT: 2 6 0.50 * addq (%rsp), %rsi +# CHECK-NEXT: 1 1 0.33 addq %rdx, %r8 + +# CHECK: Timeline view: +# CHECK-NEXT: Index 012345678 + +# CHECK: [0,0] DeER . . addq %rdi, %rsi +# CHECK-NEXT: [0,1] DeeeeeeER addq (%rsp), %rsi +# CHECK-NEXT: [0,2] .DeE----R addq %rdx, %r8 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 addq %rdi, %rsi +# CHECK-NEXT: 1. 1 1.0 0.0 0.0 addq (%rsp), %rsi +# CHECK-NEXT: 2. 1 1.0 1.0 4.0 addq %rdx, %r8 diff --git a/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-1.s b/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-1.s new file mode 100644 index 00000000000..1e4d26ae020 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-1.s @@ -0,0 +1,80 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s + +# The register move from XMM0 to XMM1 can be eliminated at register renaming +# stage. So, it should not consume pipeline resources. + +xorps %xmm0, %xmm0 +movaps %xmm0, %xmm1 +addps %xmm1, %xmm1 + +# CHECK: Iterations: 3 +# CHECK-NEXT: Instructions: 9 +# CHECK-NEXT: Total Cycles: 9 +# CHECK-NEXT: Total uOps: 9 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 0.25 xorps %xmm0, %xmm0 +# CHECK-NEXT: 1 1 1.00 movaps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 addps %xmm1, %xmm1 + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 9 +# CHECK-NEXT: Max number of mappings used: 8 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - - xorps %xmm0, %xmm0 +# CHECK-NEXT: - - - - - 1.00 - - movaps %xmm0, %xmm1 +# CHECK-NEXT: - - - 1.00 - - - - addps %xmm1, %xmm1 + +# CHECK: Timeline view: +# CHECK-NEXT: Index 012345678 + +# CHECK: [0,0] DR . . xorps %xmm0, %xmm0 +# CHECK-NEXT: [0,1] DeER . . movaps %xmm0, %xmm1 +# CHECK-NEXT: [0,2] D=eeeER . addps %xmm1, %xmm1 +# CHECK-NEXT: [1,0] D-----R . xorps %xmm0, %xmm0 +# CHECK-NEXT: [1,1] .DeE--R . movaps %xmm0, %xmm1 +# CHECK-NEXT: [1,2] .D=eeeER. addps %xmm1, %xmm1 +# CHECK-NEXT: [2,0] .D-----R. xorps %xmm0, %xmm0 +# CHECK-NEXT: [2,1] .D=eE--R. movaps %xmm0, %xmm1 +# CHECK-NEXT: [2,2] . D=eeeER addps %xmm1, %xmm1 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 0.0 0.0 3.3 xorps %xmm0, %xmm0 +# CHECK-NEXT: 1. 3 1.3 1.3 1.3 movaps %xmm0, %xmm1 +# CHECK-NEXT: 2. 3 2.0 0.0 0.0 addps %xmm1, %xmm1 diff --git a/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-2.s b/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-2.s new file mode 100644 index 00000000000..6f22cdc0b7e --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-2.s @@ -0,0 +1,121 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s + +pxor %mm0, %mm0 +movq %mm0, %mm1 + +xorps %xmm0, %xmm0 +movaps %xmm0, %xmm1 +movups %xmm1, %xmm2 +movapd %xmm2, %xmm3 +movupd %xmm3, %xmm4 +movdqa %xmm4, %xmm5 +movdqu %xmm5, %xmm0 + +# CHECK: Iterations: 3 +# CHECK-NEXT: Instructions: 27 +# CHECK-NEXT: Total Cycles: 22 +# CHECK-NEXT: Total uOps: 27 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.23 +# CHECK-NEXT: IPC: 1.23 +# CHECK-NEXT: Block RThroughput: 4.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 pxor %mm0, %mm0 +# CHECK-NEXT: 1 1 0.50 movq %mm0, %mm1 +# CHECK-NEXT: 1 0 0.25 xorps %xmm0, %xmm0 +# CHECK-NEXT: 1 1 1.00 movaps %xmm0, %xmm1 +# CHECK-NEXT: 1 1 1.00 movups %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 movapd %xmm2, %xmm3 +# CHECK-NEXT: 1 1 1.00 movupd %xmm3, %xmm4 +# CHECK-NEXT: 1 1 0.33 movdqa %xmm4, %xmm5 +# CHECK-NEXT: 1 1 0.33 movdqu %xmm5, %xmm0 + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 27 +# CHECK-NEXT: Max number of mappings used: 21 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.67 1.67 - 4.67 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 0.67 - 0.33 - - pxor %mm0, %mm0 +# CHECK-NEXT: - - 1.00 - - - - - movq %mm0, %mm1 +# CHECK-NEXT: - - - - - - - - xorps %xmm0, %xmm0 +# CHECK-NEXT: - - - - - 1.00 - - movaps %xmm0, %xmm1 +# CHECK-NEXT: - - - - - 1.00 - - movups %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movapd %xmm2, %xmm3 +# CHECK-NEXT: - - - - - 1.00 - - movupd %xmm3, %xmm4 +# CHECK-NEXT: - - - 1.00 - - - - movdqa %xmm4, %xmm5 +# CHECK-NEXT: - - 0.67 - - 0.33 - - movdqu %xmm5, %xmm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 01 + +# CHECK: [0,0] DeER . . . .. pxor %mm0, %mm0 +# CHECK-NEXT: [0,1] D=eER. . . .. movq %mm0, %mm1 +# CHECK-NEXT: [0,2] D---R. . . .. xorps %xmm0, %xmm0 +# CHECK-NEXT: [0,3] D=eER. . . .. movaps %xmm0, %xmm1 +# CHECK-NEXT: [0,4] .D=eER . . .. movups %xmm1, %xmm2 +# CHECK-NEXT: [0,5] .D==eER . . .. movapd %xmm2, %xmm3 +# CHECK-NEXT: [0,6] .D===eER . . .. movupd %xmm3, %xmm4 +# CHECK-NEXT: [0,7] .D====eER . . .. movdqa %xmm4, %xmm5 +# CHECK-NEXT: [0,8] . D====eER. . .. movdqu %xmm5, %xmm0 +# CHECK-NEXT: [1,0] . DeE----R. . .. pxor %mm0, %mm0 +# CHECK-NEXT: [1,1] . D=eE---R. . .. movq %mm0, %mm1 +# CHECK-NEXT: [1,2] . D=====ER. . .. xorps %xmm0, %xmm0 +# CHECK-NEXT: [1,3] . D====eER . .. movaps %xmm0, %xmm1 +# CHECK-NEXT: [1,4] . D=====eER . .. movups %xmm1, %xmm2 +# CHECK-NEXT: [1,5] . D======eER . .. movapd %xmm2, %xmm3 +# CHECK-NEXT: [1,6] . D=======eER . .. movupd %xmm3, %xmm4 +# CHECK-NEXT: [1,7] . D=======eER. .. movdqa %xmm4, %xmm5 +# CHECK-NEXT: [1,8] . D========eER .. movdqu %xmm5, %xmm0 +# CHECK-NEXT: [2,0] . DeE--------R .. pxor %mm0, %mm0 +# CHECK-NEXT: [2,1] . D=eE-------R .. movq %mm0, %mm1 +# CHECK-NEXT: [2,2] . D========ER .. xorps %xmm0, %xmm0 +# CHECK-NEXT: [2,3] . D========eER .. movaps %xmm0, %xmm1 +# CHECK-NEXT: [2,4] . D=========eER .. movups %xmm1, %xmm2 +# CHECK-NEXT: [2,5] . D==========eER .. movapd %xmm2, %xmm3 +# CHECK-NEXT: [2,6] . .D==========eER.. movupd %xmm3, %xmm4 +# CHECK-NEXT: [2,7] . .D===========eER. movdqa %xmm4, %xmm5 +# CHECK-NEXT: [2,8] . .D============eER movdqu %xmm5, %xmm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 1.0 1.0 4.0 pxor %mm0, %mm0 +# CHECK-NEXT: 1. 3 2.0 0.0 3.3 movq %mm0, %mm1 +# CHECK-NEXT: 2. 3 5.0 0.0 1.0 xorps %xmm0, %xmm0 +# CHECK-NEXT: 3. 3 5.3 0.7 0.0 movaps %xmm0, %xmm1 +# CHECK-NEXT: 4. 3 6.0 0.0 0.0 movups %xmm1, %xmm2 +# CHECK-NEXT: 5. 3 7.0 0.0 0.0 movapd %xmm2, %xmm3 +# CHECK-NEXT: 6. 3 7.7 0.0 0.0 movupd %xmm3, %xmm4 +# CHECK-NEXT: 7. 3 8.3 0.0 0.0 movdqa %xmm4, %xmm5 +# CHECK-NEXT: 8. 3 9.0 0.0 0.0 movdqu %xmm5, %xmm0 diff --git a/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-3.s b/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-3.s new file mode 100644 index 00000000000..e85ce5254bc --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-3.s @@ -0,0 +1,106 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s + +vxorps %xmm0, %xmm0, %xmm0 +movaps %xmm0, %xmm1 +movups %xmm1, %xmm2 +movapd %xmm2, %xmm3 +movupd %xmm3, %xmm4 +movdqa %xmm4, %xmm5 +movdqu %xmm5, %xmm0 + +# CHECK: Iterations: 3 +# CHECK-NEXT: Instructions: 21 +# CHECK-NEXT: Total Cycles: 21 +# CHECK-NEXT: Total uOps: 21 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 4.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 0.25 vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: 1 1 1.00 movaps %xmm0, %xmm1 +# CHECK-NEXT: 1 1 1.00 movups %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 movapd %xmm2, %xmm3 +# CHECK-NEXT: 1 1 1.00 movupd %xmm3, %xmm4 +# CHECK-NEXT: 1 1 0.33 movdqa %xmm4, %xmm5 +# CHECK-NEXT: 1 1 0.33 movdqu %xmm5, %xmm0 + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 21 +# CHECK-NEXT: Max number of mappings used: 17 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 - 4.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - - vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: - - - - - 1.00 - - movaps %xmm0, %xmm1 +# CHECK-NEXT: - - - - - 1.00 - - movups %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movapd %xmm2, %xmm3 +# CHECK-NEXT: - - - - - 1.00 - - movupd %xmm3, %xmm4 +# CHECK-NEXT: - - - 1.00 - - - - movdqa %xmm4, %xmm5 +# CHECK-NEXT: - - 1.00 - - - - - movdqu %xmm5, %xmm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0 + +# CHECK: [0,0] DR . . . . vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [0,1] DeER . . . . movaps %xmm0, %xmm1 +# CHECK-NEXT: [0,2] D=eER. . . . movups %xmm1, %xmm2 +# CHECK-NEXT: [0,3] D==eER . . . movapd %xmm2, %xmm3 +# CHECK-NEXT: [0,4] .D==eER . . . movupd %xmm3, %xmm4 +# CHECK-NEXT: [0,5] .D===eER . . . movdqa %xmm4, %xmm5 +# CHECK-NEXT: [0,6] .D====eER . . . movdqu %xmm5, %xmm0 +# CHECK-NEXT: [1,0] .D=====ER . . . vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [1,1] . D====eER. . . movaps %xmm0, %xmm1 +# CHECK-NEXT: [1,2] . D=====eER . . movups %xmm1, %xmm2 +# CHECK-NEXT: [1,3] . D======eER . . movapd %xmm2, %xmm3 +# CHECK-NEXT: [1,4] . D=======eER . . movupd %xmm3, %xmm4 +# CHECK-NEXT: [1,5] . D=======eER . . movdqa %xmm4, %xmm5 +# CHECK-NEXT: [1,6] . D========eER. . movdqu %xmm5, %xmm0 +# CHECK-NEXT: [2,0] . D=========ER. . vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [2,1] . D=========eER . movaps %xmm0, %xmm1 +# CHECK-NEXT: [2,2] . D=========eER . movups %xmm1, %xmm2 +# CHECK-NEXT: [2,3] . D==========eER . movapd %xmm2, %xmm3 +# CHECK-NEXT: [2,4] . D===========eER . movupd %xmm3, %xmm4 +# CHECK-NEXT: [2,5] . D============eER. movdqa %xmm4, %xmm5 +# CHECK-NEXT: [2,6] . D============eER movdqu %xmm5, %xmm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 5.3 0.0 0.0 vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: 1. 3 5.3 0.3 0.0 movaps %xmm0, %xmm1 +# CHECK-NEXT: 2. 3 6.0 0.0 0.0 movups %xmm1, %xmm2 +# CHECK-NEXT: 3. 3 7.0 0.0 0.0 movapd %xmm2, %xmm3 +# CHECK-NEXT: 4. 3 7.7 0.0 0.0 movupd %xmm3, %xmm4 +# CHECK-NEXT: 5. 3 8.3 0.0 0.0 movdqa %xmm4, %xmm5 +# CHECK-NEXT: 6. 3 9.0 0.0 0.0 movdqu %xmm5, %xmm0 diff --git a/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-4.s b/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-4.s new file mode 100644 index 00000000000..339ec06bcc8 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-4.s @@ -0,0 +1,92 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s + +xor %eax, %eax +mov %eax, %ebx +mov %ebx, %ecx +mov %ecx, %edx +mov %edx, %eax + +# CHECK: Iterations: 3 +# CHECK-NEXT: Instructions: 15 +# CHECK-NEXT: Total Cycles: 15 +# CHECK-NEXT: Total uOps: 15 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 1.3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 0.25 xorl %eax, %eax +# CHECK-NEXT: 1 1 0.33 movl %eax, %ebx +# CHECK-NEXT: 1 1 0.33 movl %ebx, %ecx +# CHECK-NEXT: 1 1 0.33 movl %ecx, %edx +# CHECK-NEXT: 1 1 0.33 movl %edx, %eax + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 18 +# CHECK-NEXT: Max number of mappings used: 15 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.33 1.33 - 1.33 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - - xorl %eax, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movl %eax, %ebx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movl %ebx, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movl %ecx, %edx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movl %edx, %eax + +# CHECK: Timeline view: +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DR . . . xorl %eax, %eax +# CHECK-NEXT: [0,1] DeER . . . movl %eax, %ebx +# CHECK-NEXT: [0,2] D=eER. . . movl %ebx, %ecx +# CHECK-NEXT: [0,3] D==eER . . movl %ecx, %edx +# CHECK-NEXT: [0,4] .D==eER . . movl %edx, %eax +# CHECK-NEXT: [1,0] .D===ER . . xorl %eax, %eax +# CHECK-NEXT: [1,1] .D===eER . . movl %eax, %ebx +# CHECK-NEXT: [1,2] .D====eER . . movl %ebx, %ecx +# CHECK-NEXT: [1,3] . D====eER. . movl %ecx, %edx +# CHECK-NEXT: [1,4] . D=====eER . movl %edx, %eax +# CHECK-NEXT: [2,0] . D======ER . xorl %eax, %eax +# CHECK-NEXT: [2,1] . D======eER . movl %eax, %ebx +# CHECK-NEXT: [2,2] . D======eER . movl %ebx, %ecx +# CHECK-NEXT: [2,3] . D=======eER. movl %ecx, %edx +# CHECK-NEXT: [2,4] . D========eER movl %edx, %eax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 3.7 0.0 0.0 xorl %eax, %eax +# CHECK-NEXT: 1. 3 4.0 0.3 0.0 movl %eax, %ebx +# CHECK-NEXT: 2. 3 4.7 0.0 0.0 movl %ebx, %ecx +# CHECK-NEXT: 3. 3 5.3 0.0 0.0 movl %ecx, %edx +# CHECK-NEXT: 4. 3 6.0 0.0 0.0 movl %edx, %eax diff --git a/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-5.s b/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-5.s new file mode 100644 index 00000000000..66ce02cb0fc --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-5.s @@ -0,0 +1,92 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s + +xor %rax, %rax +mov %rax, %rbx +mov %rbx, %rcx +mov %rcx, %rdx +mov %rdx, %rax + +# CHECK: Iterations: 3 +# CHECK-NEXT: Instructions: 15 +# CHECK-NEXT: Total Cycles: 15 +# CHECK-NEXT: Total uOps: 15 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 1.3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 0.25 xorq %rax, %rax +# CHECK-NEXT: 1 1 0.33 movq %rax, %rbx +# CHECK-NEXT: 1 1 0.33 movq %rbx, %rcx +# CHECK-NEXT: 1 1 0.33 movq %rcx, %rdx +# CHECK-NEXT: 1 1 0.33 movq %rdx, %rax + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 18 +# CHECK-NEXT: Max number of mappings used: 15 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.33 1.33 - 1.33 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - - xorq %rax, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %rax, %rbx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %rbx, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %rcx, %rdx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %rdx, %rax + +# CHECK: Timeline view: +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DR . . . xorq %rax, %rax +# CHECK-NEXT: [0,1] DeER . . . movq %rax, %rbx +# CHECK-NEXT: [0,2] D=eER. . . movq %rbx, %rcx +# CHECK-NEXT: [0,3] D==eER . . movq %rcx, %rdx +# CHECK-NEXT: [0,4] .D==eER . . movq %rdx, %rax +# CHECK-NEXT: [1,0] .D===ER . . xorq %rax, %rax +# CHECK-NEXT: [1,1] .D===eER . . movq %rax, %rbx +# CHECK-NEXT: [1,2] .D====eER . . movq %rbx, %rcx +# CHECK-NEXT: [1,3] . D====eER. . movq %rcx, %rdx +# CHECK-NEXT: [1,4] . D=====eER . movq %rdx, %rax +# CHECK-NEXT: [2,0] . D======ER . xorq %rax, %rax +# CHECK-NEXT: [2,1] . D======eER . movq %rax, %rbx +# CHECK-NEXT: [2,2] . D======eER . movq %rbx, %rcx +# CHECK-NEXT: [2,3] . D=======eER. movq %rcx, %rdx +# CHECK-NEXT: [2,4] . D========eER movq %rdx, %rax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 3.7 0.0 0.0 xorq %rax, %rax +# CHECK-NEXT: 1. 3 4.0 0.3 0.0 movq %rax, %rbx +# CHECK-NEXT: 2. 3 4.7 0.0 0.0 movq %rbx, %rcx +# CHECK-NEXT: 3. 3 5.3 0.0 0.0 movq %rcx, %rdx +# CHECK-NEXT: 4. 3 6.0 0.0 0.0 movq %rdx, %rax diff --git a/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-6.s b/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-6.s new file mode 100644 index 00000000000..70bd65681fe --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-6.s @@ -0,0 +1,98 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -register-file-stats < %s | FileCheck %s + +xor %rsi, %rsi +add %rcx, %rcx +add %rcx, %rcx +add %rcx, %rcx +add %rcx, %rcx +mov %esi, %ecx + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 600 +# CHECK-NEXT: Total Cycles: 172 +# CHECK-NEXT: Total uOps: 600 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 3.49 +# CHECK-NEXT: IPC: 3.49 +# CHECK-NEXT: Block RThroughput: 1.7 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 0.25 xorq %rsi, %rsi +# CHECK-NEXT: 1 1 0.33 addq %rcx, %rcx +# CHECK-NEXT: 1 1 0.33 addq %rcx, %rcx +# CHECK-NEXT: 1 1 0.33 addq %rcx, %rcx +# CHECK-NEXT: 1 1 0.33 addq %rcx, %rcx +# CHECK-NEXT: 1 1 0.33 movl %esi, %ecx + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 1100 +# CHECK-NEXT: Max number of mappings used: 141 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.66 1.67 - 1.67 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - - xorq %rsi, %rsi +# CHECK-NEXT: - - 0.66 0.33 - 0.01 - - addq %rcx, %rcx +# CHECK-NEXT: - - - 1.00 - - - - addq %rcx, %rcx +# CHECK-NEXT: - - - 0.33 - 0.67 - - addq %rcx, %rcx +# CHECK-NEXT: - - - 0.01 - 0.99 - - addq %rcx, %rcx +# CHECK-NEXT: - - 1.00 - - - - - movl %esi, %ecx + +# CHECK: Timeline view: +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DR . . xorq %rsi, %rsi +# CHECK-NEXT: [0,1] DeER . . addq %rcx, %rcx +# CHECK-NEXT: [0,2] D=eER. . addq %rcx, %rcx +# CHECK-NEXT: [0,3] D==eER . addq %rcx, %rcx +# CHECK-NEXT: [0,4] .D==eER . addq %rcx, %rcx +# CHECK-NEXT: [0,5] .DeE--R . movl %esi, %ecx +# CHECK-NEXT: [1,0] .D----R . xorq %rsi, %rsi +# CHECK-NEXT: [1,1] .D=eE-R . addq %rcx, %rcx +# CHECK-NEXT: [1,2] . D=eER . addq %rcx, %rcx +# CHECK-NEXT: [1,3] . D==eER . addq %rcx, %rcx +# CHECK-NEXT: [1,4] . D===eER. addq %rcx, %rcx +# CHECK-NEXT: [1,5] . DeE---R. movl %esi, %ecx +# CHECK-NEXT: [2,0] . D----R. xorq %rsi, %rsi +# CHECK-NEXT: [2,1] . DeE--R. addq %rcx, %rcx +# CHECK-NEXT: [2,2] . D=eE-R. addq %rcx, %rcx +# CHECK-NEXT: [2,3] . D==eER. addq %rcx, %rcx +# CHECK-NEXT: [2,4] . D==eER addq %rcx, %rcx +# CHECK-NEXT: [2,5] . DeE--R movl %esi, %ecx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 0.0 0.0 2.7 xorq %rsi, %rsi +# CHECK-NEXT: 1. 3 1.3 0.3 1.0 addq %rcx, %rcx +# CHECK-NEXT: 2. 3 2.0 0.0 0.3 addq %rcx, %rcx +# CHECK-NEXT: 3. 3 3.0 0.0 0.0 addq %rcx, %rcx +# CHECK-NEXT: 4. 3 3.3 0.0 0.0 addq %rcx, %rcx +# CHECK-NEXT: 5. 3 1.0 1.0 2.3 movl %esi, %ecx diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-3dnow.s b/test/tools/llvm-mca/X86/Barcelona/resources-3dnow.s new file mode 100644 index 00000000000..52a0968d1fd --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-3dnow.s @@ -0,0 +1,208 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +femms + +pavgusb %mm0, %mm2 +pavgusb (%rax), %mm2 + +pf2id %mm0, %mm2 +pf2id (%rax), %mm2 + +pf2iw %mm0, %mm2 +pf2iw (%rax), %mm2 + +pfacc %mm0, %mm2 +pfacc (%rax), %mm2 + +pfadd %mm0, %mm2 +pfadd (%rax), %mm2 + +pfcmpeq %mm0, %mm2 +pfcmpeq (%rax), %mm2 + +pfcmpge %mm0, %mm2 +pfcmpge (%rax), %mm2 + +pfcmpgt %mm0, %mm2 +pfcmpgt (%rax), %mm2 + +pfmax %mm0, %mm2 +pfmax (%rax), %mm2 + +pfmin %mm0, %mm2 +pfmin (%rax), %mm2 + +pfmul %mm0, %mm2 +pfmul (%rax), %mm2 + +pfnacc %mm0, %mm2 +pfnacc (%rax), %mm2 + +pfpnacc %mm0, %mm2 +pfpnacc (%rax), %mm2 + +pfrcp %mm0, %mm2 +pfrcp (%rax), %mm2 + +pfrcpit1 %mm0, %mm2 +pfrcpit1 (%rax), %mm2 + +pfrcpit2 %mm0, %mm2 +pfrcpit2 (%rax), %mm2 + +pfrsqit1 %mm0, %mm2 +pfrsqit1 (%rax), %mm2 + +pfrsqrt %mm0, %mm2 +pfrsqrt (%rax), %mm2 + +pfsub %mm0, %mm2 +pfsub (%rax), %mm2 + +pfsubr %mm0, %mm2 +pfsubr (%rax), %mm2 + +pi2fd %mm0, %mm2 +pi2fd (%rax), %mm2 + +pi2fw %mm0, %mm2 +pi2fw (%rax), %mm2 + +pmulhrw %mm0, %mm2 +pmulhrw (%rax), %mm2 + +prefetch (%rax) +prefetchw (%rax) + +pswapd %mm0, %mm2 +pswapd (%rax), %mm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 31 31 10.33 * * U femms +# CHECK-NEXT: 1 3 1.00 pavgusb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pavgusb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pf2id %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pf2id (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pf2iw %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pf2iw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfacc %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfacc (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfadd %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfadd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfcmpeq %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfcmpeq (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfcmpge %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfcmpge (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfcmpgt %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfcmpgt (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfmax %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfmax (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfmin %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfmin (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfmul %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfmul (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfnacc %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfnacc (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfpnacc %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfpnacc (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfrcp %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfrcp (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfrcpit1 %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfrcpit1 (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfrcpit2 %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfrcpit2 (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfrsqit1 %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfrsqit1 (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfrsqrt %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfrsqrt (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfsub %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfsub (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfsubr %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfsubr (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pi2fd %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pi2fd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pi2fw %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pi2fw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmulhrw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhrw (%rax), %mm2 +# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax) +# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax) +# CHECK-NEXT: 1 1 1.00 pswapd %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * pswapd (%rax), %mm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 12.33 54.33 - 12.33 13.00 13.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 10.33 10.33 - 10.33 - - femms +# CHECK-NEXT: - - - 1.00 - - - - pavgusb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pavgusb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pf2id %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pf2id (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pf2iw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pf2iw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfacc %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfacc (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfadd %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfadd (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfcmpeq %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfcmpeq (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfcmpge %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfcmpge (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfcmpgt %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfcmpgt (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfmax %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfmax (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfmin %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfmin (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfmul %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfmul (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfnacc %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfnacc (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfpnacc %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfpnacc (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfrcp %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrcp (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfrcpit1 %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrcpit1 (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfrcpit2 %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrcpit2 (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfrsqit1 %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrsqit1 (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfrsqrt %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrsqrt (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfsub %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfsub (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfsubr %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfsubr (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pi2fd %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pi2fd (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pi2fw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pi2fw (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmulhrw %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhrw (%rax), %mm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetch (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetchw (%rax) +# CHECK-NEXT: - - - - - 1.00 - - pswapd %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 pswapd (%rax), %mm2 diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-cmov.s b/test/tools/llvm-mca/X86/Barcelona/resources-cmov.s new file mode 100644 index 00000000000..e41571428d9 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-cmov.s @@ -0,0 +1,323 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +cmovow %si, %di +cmovnow %si, %di +cmovbw %si, %di +cmovaew %si, %di +cmovew %si, %di +cmovnew %si, %di +cmovbew %si, %di +cmovaw %si, %di +cmovsw %si, %di +cmovnsw %si, %di +cmovpw %si, %di +cmovnpw %si, %di +cmovlw %si, %di +cmovgew %si, %di +cmovlew %si, %di +cmovgw %si, %di + +cmovow (%rax), %di +cmovnow (%rax), %di +cmovbw (%rax), %di +cmovaew (%rax), %di +cmovew (%rax), %di +cmovnew (%rax), %di +cmovbew (%rax), %di +cmovaw (%rax), %di +cmovsw (%rax), %di +cmovnsw (%rax), %di +cmovpw (%rax), %di +cmovnpw (%rax), %di +cmovlw (%rax), %di +cmovgew (%rax), %di +cmovlew (%rax), %di +cmovgw (%rax), %di + +cmovol %esi, %edi +cmovnol %esi, %edi +cmovbl %esi, %edi +cmovael %esi, %edi +cmovel %esi, %edi +cmovnel %esi, %edi +cmovbel %esi, %edi +cmoval %esi, %edi +cmovsl %esi, %edi +cmovnsl %esi, %edi +cmovpl %esi, %edi +cmovnpl %esi, %edi +cmovll %esi, %edi +cmovgel %esi, %edi +cmovlel %esi, %edi +cmovgl %esi, %edi + +cmovol (%rax), %edi +cmovnol (%rax), %edi +cmovbl (%rax), %edi +cmovael (%rax), %edi +cmovel (%rax), %edi +cmovnel (%rax), %edi +cmovbel (%rax), %edi +cmoval (%rax), %edi +cmovsl (%rax), %edi +cmovnsl (%rax), %edi +cmovpl (%rax), %edi +cmovnpl (%rax), %edi +cmovll (%rax), %edi +cmovgel (%rax), %edi +cmovlel (%rax), %edi +cmovgl (%rax), %edi + +cmovoq %rsi, %rdi +cmovnoq %rsi, %rdi +cmovbq %rsi, %rdi +cmovaeq %rsi, %rdi +cmoveq %rsi, %rdi +cmovneq %rsi, %rdi +cmovbeq %rsi, %rdi +cmovaq %rsi, %rdi +cmovsq %rsi, %rdi +cmovnsq %rsi, %rdi +cmovpq %rsi, %rdi +cmovnpq %rsi, %rdi +cmovlq %rsi, %rdi +cmovgeq %rsi, %rdi +cmovleq %rsi, %rdi +cmovgq %rsi, %rdi + +cmovoq (%rax), %rdi +cmovnoq (%rax), %rdi +cmovbq (%rax), %rdi +cmovaeq (%rax), %rdi +cmoveq (%rax), %rdi +cmovneq (%rax), %rdi +cmovbeq (%rax), %rdi +cmovaq (%rax), %rdi +cmovsq (%rax), %rdi +cmovnsq (%rax), %rdi +cmovpq (%rax), %rdi +cmovnpq (%rax), %rdi +cmovlq (%rax), %rdi +cmovgeq (%rax), %rdi +cmovleq (%rax), %rdi +cmovgq (%rax), %rdi + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 2 0.67 cmovow %si, %di +# CHECK-NEXT: 2 2 0.67 cmovnow %si, %di +# CHECK-NEXT: 2 2 0.67 cmovbw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovaew %si, %di +# CHECK-NEXT: 2 2 0.67 cmovew %si, %di +# CHECK-NEXT: 2 2 0.67 cmovnew %si, %di +# CHECK-NEXT: 3 3 1.00 cmovbew %si, %di +# CHECK-NEXT: 3 3 1.00 cmovaw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovsw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovnsw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovpw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovnpw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovlw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovgew %si, %di +# CHECK-NEXT: 2 2 0.67 cmovlew %si, %di +# CHECK-NEXT: 2 2 0.67 cmovgw %si, %di +# CHECK-NEXT: 3 7 0.67 * cmovow (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovnow (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovbw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovaew (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovew (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovnew (%rax), %di +# CHECK-NEXT: 4 8 1.00 * cmovbew (%rax), %di +# CHECK-NEXT: 4 8 1.00 * cmovaw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovsw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovnsw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovpw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovnpw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovlw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovgew (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovlew (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovgw (%rax), %di +# CHECK-NEXT: 2 2 0.67 cmovol %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovnol %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovbl %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovael %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovel %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovnel %esi, %edi +# CHECK-NEXT: 3 3 1.00 cmovbel %esi, %edi +# CHECK-NEXT: 3 3 1.00 cmoval %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovsl %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovnsl %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovpl %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovnpl %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovll %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovgel %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovlel %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovgl %esi, %edi +# CHECK-NEXT: 3 7 0.67 * cmovol (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovnol (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovbl (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovael (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovel (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovnel (%rax), %edi +# CHECK-NEXT: 4 8 1.00 * cmovbel (%rax), %edi +# CHECK-NEXT: 4 8 1.00 * cmoval (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovsl (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovnsl (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovpl (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovnpl (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovll (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovgel (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovlel (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovgl (%rax), %edi +# CHECK-NEXT: 2 2 0.67 cmovoq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovnoq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovbq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovaeq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmoveq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovneq %rsi, %rdi +# CHECK-NEXT: 3 3 1.00 cmovbeq %rsi, %rdi +# CHECK-NEXT: 3 3 1.00 cmovaq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovsq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovnsq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovpq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovnpq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovlq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovgeq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovleq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovgq %rsi, %rdi +# CHECK-NEXT: 3 7 0.67 * cmovoq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovnoq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovbq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovaeq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmoveq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovneq (%rax), %rdi +# CHECK-NEXT: 4 8 1.00 * cmovbeq (%rax), %rdi +# CHECK-NEXT: 4 8 1.00 * cmovaq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovsq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovnsq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovpq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovnpq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovlq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovgeq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovleq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovgq (%rax), %rdi + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 86.00 32.00 - 86.00 24.00 24.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovow %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnow %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovbw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovaew %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovew %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnew %si, %di +# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovbew %si, %di +# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovaw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovsw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnsw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovpw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnpw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovlw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgew %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovlew %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovow (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnow (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovbw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovaew (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovew (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnew (%rax), %di +# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovbew (%rax), %di +# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovaw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovsw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnsw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovpw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnpw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovlw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgew (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovlew (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovol %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnol %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovbl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovael %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovel %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnel %esi, %edi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovbel %esi, %edi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmoval %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovsl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnsl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovpl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnpl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovll %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgel %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovlel %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovol (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnol (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovbl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovael (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovel (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnel (%rax), %edi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovbel (%rax), %edi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmoval (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovsl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnsl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovpl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnpl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovll (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgel (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovlel (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovoq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnoq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovbq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovaeq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmoveq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovneq %rsi, %rdi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovbeq %rsi, %rdi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovaq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovsq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnsq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovpq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnpq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovlq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgeq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovleq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovoq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnoq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovbq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovaeq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmoveq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovneq (%rax), %rdi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovbeq (%rax), %rdi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovaq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovsq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnsq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovpq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnpq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovlq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgeq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovleq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgq (%rax), %rdi diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-cmpxchg.s b/test/tools/llvm-mca/X86/Barcelona/resources-cmpxchg.s new file mode 100644 index 00000000000..19a220702b1 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-cmpxchg.s @@ -0,0 +1,36 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +cmpxchg8b (%rax) +cmpxchg16b (%rax) + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 3 6 1.00 * * cmpxchg8b (%rax) +# CHECK-NEXT: 3 6 1.00 * * cmpxchg16b (%rax) + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 0.67 0.67 2.00 0.67 2.00 2.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 cmpxchg8b (%rax) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 cmpxchg16b (%rax) diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-lea.s b/test/tools/llvm-mca/X86/Barcelona/resources-lea.s new file mode 100644 index 00000000000..455fbe0411e --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-lea.s @@ -0,0 +1,437 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +lea 0(), %cx +lea 0(), %ecx +lea 0(), %rcx +lea (%eax), %cx +lea (%eax), %ecx +lea (%eax), %rcx +lea (%rax), %cx +lea (%rax), %ecx +lea (%rax), %rcx +lea (, %ebx), %cx +lea (, %ebx), %ecx +lea (, %ebx), %rcx +lea (, %rbx), %cx +lea (, %rbx), %ecx +lea (, %rbx), %rcx +lea (, %ebx, 1), %cx +lea (, %ebx, 1), %ecx +lea (, %ebx, 1), %rcx +lea (, %rbx, 1), %cx +lea (, %rbx, 1), %ecx +lea (, %rbx, 1), %rcx +lea (, %ebx, 2), %cx +lea (, %ebx, 2), %ecx +lea (, %ebx, 2), %rcx +lea (, %rbx, 2), %cx +lea (, %rbx, 2), %ecx +lea (, %rbx, 2), %rcx +lea (%eax, %ebx), %cx +lea (%eax, %ebx), %ecx +lea (%eax, %ebx), %rcx +lea (%rax, %rbx), %cx +lea (%rax, %rbx), %ecx +lea (%rax, %rbx), %rcx +lea (%eax, %ebx, 1), %cx +lea (%eax, %ebx, 1), %ecx +lea (%eax, %ebx, 1), %rcx +lea (%rax, %rbx, 1), %cx +lea (%rax, %rbx, 1), %ecx +lea (%rax, %rbx, 1), %rcx +lea (%eax, %ebx, 2), %cx +lea (%eax, %ebx, 2), %ecx +lea (%eax, %ebx, 2), %rcx +lea (%rax, %rbx, 2), %cx +lea (%rax, %rbx, 2), %ecx +lea (%rax, %rbx, 2), %rcx + +lea -16(), %cx +lea -16(), %ecx +lea -16(), %rcx +lea -16(%eax), %cx +lea -16(%eax), %ecx +lea -16(%eax), %rcx +lea -16(%rax), %cx +lea -16(%rax), %ecx +lea -16(%rax), %rcx +lea -16(, %ebx), %cx +lea -16(, %ebx), %ecx +lea -16(, %ebx), %rcx +lea -16(, %rbx), %cx +lea -16(, %rbx), %ecx +lea -16(, %rbx), %rcx +lea -16(, %ebx, 1), %cx +lea -16(, %ebx, 1), %ecx +lea -16(, %ebx, 1), %rcx +lea -16(, %rbx, 1), %cx +lea -16(, %rbx, 1), %ecx +lea -16(, %rbx, 1), %rcx +lea -16(, %ebx, 2), %cx +lea -16(, %ebx, 2), %ecx +lea -16(, %ebx, 2), %rcx +lea -16(, %rbx, 2), %cx +lea -16(, %rbx, 2), %ecx +lea -16(, %rbx, 2), %rcx +lea -16(%eax, %ebx), %cx +lea -16(%eax, %ebx), %ecx +lea -16(%eax, %ebx), %rcx +lea -16(%rax, %rbx), %cx +lea -16(%rax, %rbx), %ecx +lea -16(%rax, %rbx), %rcx +lea -16(%eax, %ebx, 1), %cx +lea -16(%eax, %ebx, 1), %ecx +lea -16(%eax, %ebx, 1), %rcx +lea -16(%rax, %rbx, 1), %cx +lea -16(%rax, %rbx, 1), %ecx +lea -16(%rax, %rbx, 1), %rcx +lea -16(%eax, %ebx, 2), %cx +lea -16(%eax, %ebx, 2), %ecx +lea -16(%eax, %ebx, 2), %rcx +lea -16(%rax, %rbx, 2), %cx +lea -16(%rax, %rbx, 2), %ecx +lea -16(%rax, %rbx, 2), %rcx + +lea 1024(), %cx +lea 1024(), %ecx +lea 1024(), %rcx +lea 1024(%eax), %cx +lea 1024(%eax), %ecx +lea 1024(%eax), %rcx +lea 1024(%rax), %cx +lea 1024(%rax), %ecx +lea 1024(%rax), %rcx +lea 1024(, %ebx), %cx +lea 1024(, %ebx), %ecx +lea 1024(, %ebx), %rcx +lea 1024(, %rbx), %cx +lea 1024(, %rbx), %ecx +lea 1024(, %rbx), %rcx +lea 1024(, %ebx, 1), %cx +lea 1024(, %ebx, 1), %ecx +lea 1024(, %ebx, 1), %rcx +lea 1024(, %rbx, 1), %cx +lea 1024(, %rbx, 1), %ecx +lea 1024(, %rbx, 1), %rcx +lea 1024(, %ebx, 2), %cx +lea 1024(, %ebx, 2), %ecx +lea 1024(, %ebx, 2), %rcx +lea 1024(, %rbx, 2), %cx +lea 1024(, %rbx, 2), %ecx +lea 1024(, %rbx, 2), %rcx +lea 1024(%eax, %ebx), %cx +lea 1024(%eax, %ebx), %ecx +lea 1024(%eax, %ebx), %rcx +lea 1024(%rax, %rbx), %cx +lea 1024(%rax, %rbx), %ecx +lea 1024(%rax, %rbx), %rcx +lea 1024(%eax, %ebx, 1), %cx +lea 1024(%eax, %ebx, 1), %ecx +lea 1024(%eax, %ebx, 1), %rcx +lea 1024(%rax, %rbx, 1), %cx +lea 1024(%rax, %rbx, 1), %ecx +lea 1024(%rax, %rbx, 1), %rcx +lea 1024(%eax, %ebx, 2), %cx +lea 1024(%eax, %ebx, 2), %ecx +lea 1024(%eax, %ebx, 2), %rcx +lea 1024(%rax, %rbx, 2), %cx +lea 1024(%rax, %rbx, 2), %ecx +lea 1024(%rax, %rbx, 2), %rcx + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.50 leaw 0, %cx +# CHECK-NEXT: 1 1 0.50 leal 0, %ecx +# CHECK-NEXT: 1 1 0.50 leaq 0, %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%eax), %cx +# CHECK-NEXT: 1 1 0.50 leal (%eax), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%eax), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%rax), %cx +# CHECK-NEXT: 1 1 0.50 leal (%rax), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%rax), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal (,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal (,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal (,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal (,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (,%ebx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal (,%ebx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (,%ebx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (,%rbx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal (,%rbx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (,%rbx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%eax,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal (%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%rax,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal (%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%eax,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal (%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%rax,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal (%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%eax,%ebx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal (%eax,%ebx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%eax,%ebx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%rax,%rbx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal (%rax,%rbx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%rax,%rbx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16, %cx +# CHECK-NEXT: 1 1 0.50 leal -16, %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16, %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%eax), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%eax), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%eax), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%rax), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%rax), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%rax), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(,%ebx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(,%ebx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(,%ebx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(,%rbx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(,%rbx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(,%rbx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%eax,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%rax,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%eax,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%rax,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%eax,%ebx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%eax,%ebx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%eax,%ebx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%rax,%rbx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%rax,%rbx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%rax,%rbx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024, %cx +# CHECK-NEXT: 1 1 0.50 leal 1024, %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024, %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%eax), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%eax), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%eax), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%rax), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%rax), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%rax), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(,%ebx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(,%ebx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(,%ebx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(,%rbx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(,%rbx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(,%rbx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%eax,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%rax,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%eax,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%rax,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%eax,%ebx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%eax,%ebx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%eax,%ebx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%rax,%rbx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%rax,%rbx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%rax,%rbx,2), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 67.50 67.50 - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 0, %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 0, %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 0, %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%eax), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%eax), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%eax), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%rax), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%rax), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%rax), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%ebx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%ebx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%ebx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%rbx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%rbx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%rbx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%eax,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%eax,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%eax,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%rax,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%rax,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%rax,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%eax,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%eax,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%eax,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%rax,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%rax,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%rax,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%eax,%ebx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%eax,%ebx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%eax,%ebx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%rax,%rbx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%rax,%rbx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%rax,%rbx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16, %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16, %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16, %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%eax), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%eax), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%eax), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%rax), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%rax), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%rax), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%ebx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%ebx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%ebx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%rbx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%rbx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%rbx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%eax,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%eax,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%eax,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%rax,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%rax,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%rax,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%eax,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%eax,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%eax,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%rax,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%rax,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%rax,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%eax,%ebx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%eax,%ebx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%eax,%ebx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%rax,%rbx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%rax,%rbx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%rax,%rbx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024, %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024, %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024, %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%eax), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%eax), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%eax), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%rax), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%rax), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%rax), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%ebx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%ebx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%ebx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%rbx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%rbx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%rbx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%eax,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%eax,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%eax,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%rax,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%rax,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%rax,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%eax,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%eax,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%eax,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%rax,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%rax,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%rax,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%eax,%ebx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%eax,%ebx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%eax,%ebx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%rax,%rbx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%rax,%rbx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%rax,%rbx,2), %rcx diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-lzcnt.s b/test/tools/llvm-mca/X86/Barcelona/resources-lzcnt.s new file mode 100644 index 00000000000..6ac0945d4d8 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-lzcnt.s @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +lzcntw %cx, %cx +lzcntw (%rax), %cx + +lzcntl %eax, %ecx +lzcntl (%rax), %ecx + +lzcntq %rax, %rcx +lzcntq (%rax), %rcx + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 lzcntw %cx, %cx +# CHECK-NEXT: 2 8 1.00 * lzcntw (%rax), %cx +# CHECK-NEXT: 1 3 1.00 lzcntl %eax, %ecx +# CHECK-NEXT: 2 8 1.00 * lzcntl (%rax), %ecx +# CHECK-NEXT: 1 3 1.00 lzcntq %rax, %rcx +# CHECK-NEXT: 2 8 1.00 * lzcntq (%rax), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 6.00 - - 1.50 1.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - lzcntw %cx, %cx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 lzcntw (%rax), %cx +# CHECK-NEXT: - - - 1.00 - - - - lzcntl %eax, %ecx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 lzcntl (%rax), %ecx +# CHECK-NEXT: - - - 1.00 - - - - lzcntq %rax, %rcx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 lzcntq (%rax), %rcx diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-mmx.s b/test/tools/llvm-mca/X86/Barcelona/resources-mmx.s new file mode 100644 index 00000000000..8c9644b6494 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-mmx.s @@ -0,0 +1,393 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +emms + +movd %eax, %mm2 +movd (%rax), %mm2 + +movd %mm0, %ecx +movd %mm0, (%rax) + +movq %rax, %mm2 +movq (%rax), %mm2 + +movq %mm0, %rcx +movq %mm0, (%rax) + +packsswb %mm0, %mm2 +packsswb (%rax), %mm2 + +packssdw %mm0, %mm2 +packssdw (%rax), %mm2 + +packuswb %mm0, %mm2 +packuswb (%rax), %mm2 + +paddb %mm0, %mm2 +paddb (%rax), %mm2 + +paddd %mm0, %mm2 +paddd (%rax), %mm2 + +paddsb %mm0, %mm2 +paddsb (%rax), %mm2 + +paddsw %mm0, %mm2 +paddsw (%rax), %mm2 + +paddusb %mm0, %mm2 +paddusb (%rax), %mm2 + +paddusw %mm0, %mm2 +paddusw (%rax), %mm2 + +paddw %mm0, %mm2 +paddw (%rax), %mm2 + +pand %mm0, %mm2 +pand (%rax), %mm2 + +pandn %mm0, %mm2 +pandn (%rax), %mm2 + +pcmpeqb %mm0, %mm2 +pcmpeqb (%rax), %mm2 + +pcmpeqd %mm0, %mm2 +pcmpeqd (%rax), %mm2 + +pcmpeqw %mm0, %mm2 +pcmpeqw (%rax), %mm2 + +pcmpgtb %mm0, %mm2 +pcmpgtb (%rax), %mm2 + +pcmpgtd %mm0, %mm2 +pcmpgtd (%rax), %mm2 + +pcmpgtw %mm0, %mm2 +pcmpgtw (%rax), %mm2 + +pmaddwd %mm0, %mm2 +pmaddwd (%rax), %mm2 + +pmulhw %mm0, %mm2 +pmulhw (%rax), %mm2 + +pmullw %mm0, %mm2 +pmullw (%rax), %mm2 + +por %mm0, %mm2 +por (%rax), %mm2 + +pslld $1, %mm2 +pslld %mm0, %mm2 +pslld (%rax), %mm2 + +psllq $1, %mm2 +psllq %mm0, %mm2 +psllq (%rax), %mm2 + +psllw $1, %mm2 +psllw %mm0, %mm2 +psllw (%rax), %mm2 + +psrad $1, %mm2 +psrad %mm0, %mm2 +psrad (%rax), %mm2 + +psraw $1, %mm2 +psraw %mm0, %mm2 +psraw (%rax), %mm2 + +psrld $1, %mm2 +psrld %mm0, %mm2 +psrld (%rax), %mm2 + +psrlq $1, %mm2 +psrlq %mm0, %mm2 +psrlq (%rax), %mm2 + +psrlw $1, %mm2 +psrlw %mm0, %mm2 +psrlw (%rax), %mm2 + +psubb %mm0, %mm2 +psubb (%rax), %mm2 + +psubd %mm0, %mm2 +psubd (%rax), %mm2 + +psubsb %mm0, %mm2 +psubsb (%rax), %mm2 + +psubsw %mm0, %mm2 +psubsw (%rax), %mm2 + +psubusb %mm0, %mm2 +psubusb (%rax), %mm2 + +psubusw %mm0, %mm2 +psubusw (%rax), %mm2 + +psubw %mm0, %mm2 +psubw (%rax), %mm2 + +punpckhbw %mm0, %mm2 +punpckhbw (%rax), %mm2 + +punpckhdq %mm0, %mm2 +punpckhdq (%rax), %mm2 + +punpckhwd %mm0, %mm2 +punpckhwd (%rax), %mm2 + +punpcklbw %mm0, %mm2 +punpcklbw (%rax), %mm2 + +punpckldq %mm0, %mm2 +punpckldq (%rax), %mm2 + +punpcklwd %mm0, %mm2 +punpcklwd (%rax), %mm2 + +pxor %mm0, %mm2 +pxor (%rax), %mm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 31 31 10.33 * * U emms +# CHECK-NEXT: 1 1 1.00 movd %eax, %mm2 +# CHECK-NEXT: 1 5 0.50 * movd (%rax), %mm2 +# CHECK-NEXT: 1 2 1.00 movd %mm0, %ecx +# CHECK-NEXT: 1 1 1.00 * U movd %mm0, (%rax) +# CHECK-NEXT: 1 1 1.00 movq %rax, %mm2 +# CHECK-NEXT: 1 5 0.50 * movq (%rax), %mm2 +# CHECK-NEXT: 1 2 1.00 movq %mm0, %rcx +# CHECK-NEXT: 1 1 1.00 * movq %mm0, (%rax) +# CHECK-NEXT: 1 1 1.00 packsswb %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * packsswb (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 packssdw %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * packssdw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 packuswb %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * packuswb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddd %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddsb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddsb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddsw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddsw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddusb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddusb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddusw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddusw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddw (%rax), %mm2 +# CHECK-NEXT: 1 1 0.33 pand %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * pand (%rax), %mm2 +# CHECK-NEXT: 1 1 0.33 pandn %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * pandn (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpeqb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pcmpeqb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpeqd %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pcmpeqd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpeqw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pcmpeqw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpgtb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pcmpgtb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpgtd %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pcmpgtd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpgtw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pcmpgtw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmaddwd %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmaddwd (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmulhw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmullw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmullw (%rax), %mm2 +# CHECK-NEXT: 1 1 0.33 por %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * por (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 pslld $1, %mm2 +# CHECK-NEXT: 1 1 1.00 pslld %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * pslld (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psllq $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psllq %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psllq (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psllw $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psllw %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psllw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psrad $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psrad %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psrad (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psraw $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psraw %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psraw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psrld $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psrld %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psrld (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psrlq $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psrlq %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psrlq (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psrlw $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psrlw %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psrlw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubd %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubsb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubsb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubsw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubsw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubusb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubusb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubusw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubusw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 punpckhbw %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * punpckhbw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 punpckhdq %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * punpckhdq (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 punpckhwd %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * punpckhwd (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 punpcklbw %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * punpcklbw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 punpckldq %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * punpckldq (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 punpcklwd %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * punpcklwd (%rax), %mm2 +# CHECK-NEXT: 1 1 0.33 pxor %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * pxor (%rax), %mm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 21.00 53.00 2.00 57.00 24.00 24.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 10.33 10.33 - 10.33 - - emms +# CHECK-NEXT: - - - - - 1.00 - - movd %eax, %mm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movd (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - movd %mm0, %ecx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movd %mm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 - - movq %rax, %mm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movq (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - movq %mm0, %rcx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movq %mm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 - - packsswb %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 packsswb (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - packssdw %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 packssdw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - packuswb %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 packuswb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddd %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddd (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddsb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddsb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddsw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddsw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddusb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddusb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddusw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddusw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddw (%rax), %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pand %mm0, %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pand (%rax), %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pandn %mm0, %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pandn (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpeqb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqd %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpeqd (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpeqw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpgtb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtd %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpgtd (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpgtw (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmaddwd %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmaddwd (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmulhw %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhw (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmullw %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmullw (%rax), %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - por %mm0, %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 por (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - pslld $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - pslld %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 pslld (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psllq $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psllq %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psllq (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psllw $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psllw %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psllw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrad $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrad %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psrad (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psraw $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psraw %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psraw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrld $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrld %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psrld (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrlq $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrlq %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psrlq (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrlw $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrlw %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psrlw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubd %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubd (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubsb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubsb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubsw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubsw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubusb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubusb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubusw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubusw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - punpckhbw %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpckhbw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - punpckhdq %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpckhdq (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - punpckhwd %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpckhwd (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - punpcklbw %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpcklbw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - punpckldq %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpckldq (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - punpcklwd %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpcklwd (%rax), %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pxor %mm0, %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pxor (%rax), %mm2 diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-popcnt.s b/test/tools/llvm-mca/X86/Barcelona/resources-popcnt.s new file mode 100644 index 00000000000..c24ce8869f9 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-popcnt.s @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +popcntw %cx, %cx +popcntw (%rax), %cx + +popcntl %eax, %ecx +popcntl (%rax), %ecx + +popcntq %rax, %rcx +popcntq (%rax), %rcx + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 popcntw %cx, %cx +# CHECK-NEXT: 2 9 1.00 * popcntw (%rax), %cx +# CHECK-NEXT: 1 3 1.00 popcntl %eax, %ecx +# CHECK-NEXT: 2 9 1.00 * popcntl (%rax), %ecx +# CHECK-NEXT: 1 3 1.00 popcntq %rax, %rcx +# CHECK-NEXT: 2 9 1.00 * popcntq (%rax), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 6.00 - - 1.50 1.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - popcntw %cx, %cx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 popcntw (%rax), %cx +# CHECK-NEXT: - - - 1.00 - - - - popcntl %eax, %ecx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 popcntl (%rax), %ecx +# CHECK-NEXT: - - - 1.00 - - - - popcntq %rax, %rcx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 popcntq (%rax), %rcx diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-prefetchw.s b/test/tools/llvm-mca/X86/Barcelona/resources-prefetchw.s new file mode 100644 index 00000000000..b44b28c3725 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-prefetchw.s @@ -0,0 +1,36 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +prefetch (%rax) +prefetchw (%rax) + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax) +# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax) + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - - - - 1.00 1.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetch (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetchw (%rax) diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s b/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s new file mode 100644 index 00000000000..4e6cc031e63 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s @@ -0,0 +1,461 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +addps %xmm0, %xmm2 +addps (%rax), %xmm2 + +addss %xmm0, %xmm2 +addss (%rax), %xmm2 + +andnps %xmm0, %xmm2 +andnps (%rax), %xmm2 + +andps %xmm0, %xmm2 +andps (%rax), %xmm2 + +cmpps $0, %xmm0, %xmm2 +cmpps $0, (%rax), %xmm2 + +cmpss $0, %xmm0, %xmm2 +cmpss $0, (%rax), %xmm2 + +comiss %xmm0, %xmm1 +comiss (%rax), %xmm1 + +cvtpi2ps %mm0, %xmm2 +cvtpi2ps (%rax), %xmm2 + +cvtps2pi %xmm0, %mm2 +cvtps2pi (%rax), %mm2 + +cvtsi2ss %ecx, %xmm2 +cvtsi2ss %rcx, %xmm2 +cvtsi2ss (%rax), %xmm2 +cvtsi2ss (%rax), %xmm2 + +cvtss2si %xmm0, %ecx +cvtss2si %xmm0, %rcx +cvtss2si (%rax), %ecx +cvtss2si (%rax), %rcx + +cvttps2pi %xmm0, %mm2 +cvttps2pi (%rax), %mm2 + +cvttss2si %xmm0, %ecx +cvttss2si %xmm0, %rcx +cvttss2si (%rax), %ecx +cvttss2si (%rax), %rcx + +divps %xmm0, %xmm2 +divps (%rax), %xmm2 + +divss %xmm0, %xmm2 +divss (%rax), %xmm2 + +ldmxcsr (%rax) + +maskmovq %mm0, %mm1 + +maxps %xmm0, %xmm2 +maxps (%rax), %xmm2 + +maxss %xmm0, %xmm2 +maxss (%rax), %xmm2 + +minps %xmm0, %xmm2 +minps (%rax), %xmm2 + +minss %xmm0, %xmm2 +minss (%rax), %xmm2 + +movaps %xmm0, %xmm2 +movaps %xmm0, (%rax) +movaps (%rax), %xmm2 + +movhlps %xmm0, %xmm2 +movlhps %xmm0, %xmm2 + +movhps %xmm0, (%rax) +movhps (%rax), %xmm2 + +movlps %xmm0, (%rax) +movlps (%rax), %xmm2 + +movmskps %xmm0, %rcx + +movntps %xmm0, (%rax) +movntq %mm0, (%rax) + +movss %xmm0, %xmm2 +movss %xmm0, (%rax) +movss (%rax), %xmm2 + +movups %xmm0, %xmm2 +movups %xmm0, (%rax) +movups (%rax), %xmm2 + +mulps %xmm0, %xmm2 +mulps (%rax), %xmm2 + +mulss %xmm0, %xmm2 +mulss (%rax), %xmm2 + +orps %xmm0, %xmm2 +orps (%rax), %xmm2 + +pavgb %mm0, %mm2 +pavgb (%rax), %mm2 + +pavgw %mm0, %mm2 +pavgw (%rax), %mm2 + +pextrw $1, %mm0, %rcx + +pinsrw $1, %rax, %mm2 +pinsrw $1, (%rax), %mm2 + +pmaxsw %mm0, %mm2 +pmaxsw (%rax), %mm2 + +pmaxub %mm0, %mm2 +pmaxub (%rax), %mm2 + +pminsw %mm0, %mm2 +pminsw (%rax), %mm2 + +pminub %mm0, %mm2 +pminub (%rax), %mm2 + +pmovmskb %mm0, %rcx + +pmulhuw %mm0, %mm2 +pmulhuw (%rax), %mm2 + +prefetcht0 (%rax) +prefetcht1 (%rax) +prefetcht2 (%rax) +prefetchnta (%rax) + +psadbw %mm0, %mm2 +psadbw (%rax), %mm2 + +pshufw $1, %mm0, %mm2 +pshufw $1, (%rax), %mm2 + +rcpps %xmm0, %xmm2 +rcpps (%rax), %xmm2 + +rcpss %xmm0, %xmm2 +rcpss (%rax), %xmm2 + +rsqrtps %xmm0, %xmm2 +rsqrtps (%rax), %xmm2 + +rsqrtss %xmm0, %xmm2 +rsqrtss (%rax), %xmm2 + +sfence + +shufps $1, %xmm0, %xmm2 +shufps $1, (%rax), %xmm2 + +sqrtps %xmm0, %xmm2 +sqrtps (%rax), %xmm2 + +sqrtss %xmm0, %xmm2 +sqrtss (%rax), %xmm2 + +stmxcsr (%rax) + +subps %xmm0, %xmm2 +subps (%rax), %xmm2 + +subss %xmm0, %xmm2 +subss (%rax), %xmm2 + +ucomiss %xmm0, %xmm1 +ucomiss (%rax), %xmm1 + +unpckhps %xmm0, %xmm2 +unpckhps (%rax), %xmm2 + +unpcklps %xmm0, %xmm2 +unpcklps (%rax), %xmm2 + +xorps %xmm0, %xmm2 +xorps (%rax), %xmm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * addps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 addss %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * addss (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 andnps %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * andnps (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 andps %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * andps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 cmpeqps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cmpeqps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 cmpeqss %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cmpeqss (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 comiss %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * comiss (%rax), %xmm1 +# CHECK-NEXT: 1 3 1.00 cvtpi2ps %mm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cvtpi2ps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 cvtps2pi %xmm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * cvtps2pi (%rax), %mm2 +# CHECK-NEXT: 3 5 2.00 cvtsi2ss %ecx, %xmm2 +# CHECK-NEXT: 3 5 2.00 cvtsi2ss %rcx, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtsi2ssl (%rax), %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtsi2ssl (%rax), %xmm2 +# CHECK-NEXT: 2 5 1.00 cvtss2si %xmm0, %ecx +# CHECK-NEXT: 2 5 1.00 cvtss2si %xmm0, %rcx +# CHECK-NEXT: 3 9 1.00 * cvtss2si (%rax), %ecx +# CHECK-NEXT: 3 9 1.00 * cvtss2si (%rax), %rcx +# CHECK-NEXT: 1 3 1.00 cvttps2pi %xmm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * cvttps2pi (%rax), %mm2 +# CHECK-NEXT: 2 5 1.00 cvttss2si %xmm0, %ecx +# CHECK-NEXT: 2 5 1.00 cvttss2si %xmm0, %rcx +# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %ecx +# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %rcx +# CHECK-NEXT: 1 14 14.00 divps %xmm0, %xmm2 +# CHECK-NEXT: 2 20 14.00 * divps (%rax), %xmm2 +# CHECK-NEXT: 1 14 14.00 divss %xmm0, %xmm2 +# CHECK-NEXT: 2 20 14.00 * divss (%rax), %xmm2 +# CHECK-NEXT: 4 5 1.00 * * U ldmxcsr (%rax) +# CHECK-NEXT: 1 1 1.00 * * U maskmovq %mm0, %mm1 +# CHECK-NEXT: 1 3 1.00 maxps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * maxps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 maxss %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * maxss (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 minps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * minps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 minss %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * minss (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movaps %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movaps %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movaps (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movhlps %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 movlhps %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movhps %xmm0, (%rax) +# CHECK-NEXT: 2 7 1.00 * movhps (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 * movlps %xmm0, (%rax) +# CHECK-NEXT: 2 7 1.00 * movlps (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 movmskps %xmm0, %ecx +# CHECK-NEXT: 1 1 1.00 * movntps %xmm0, (%rax) +# CHECK-NEXT: 1 1 1.00 * * U movntq %mm0, (%rax) +# CHECK-NEXT: 1 1 1.00 movss %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movss %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movss (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movups %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movups %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movups (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 mulps %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * mulps (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 mulss %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * mulss (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 orps %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * orps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 pavgb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pavgb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pavgw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pavgw (%rax), %mm2 +# CHECK-NEXT: 2 3 1.00 pextrw $1, %mm0, %ecx +# CHECK-NEXT: 2 2 1.00 pinsrw $1, %eax, %mm2 +# CHECK-NEXT: 2 7 0.50 * pinsrw $1, (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pmaxsw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pmaxsw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pmaxub %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pmaxub (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pminsw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pminsw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pminub %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pminub (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 pmovmskb %mm0, %ecx +# CHECK-NEXT: 1 5 1.00 pmulhuw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhuw (%rax), %mm2 +# CHECK-NEXT: 1 5 0.50 * * prefetcht0 (%rax) +# CHECK-NEXT: 1 5 0.50 * * prefetcht1 (%rax) +# CHECK-NEXT: 1 5 0.50 * * prefetcht2 (%rax) +# CHECK-NEXT: 1 5 0.50 * * prefetchnta (%rax) +# CHECK-NEXT: 1 5 1.00 psadbw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * psadbw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 pshufw $1, %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * pshufw $1, (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 rcpps %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * rcpps (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 rcpss %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * rcpss (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 rsqrtps %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * rsqrtps (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 rsqrtss %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * rsqrtss (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 * * U sfence +# CHECK-NEXT: 1 1 1.00 shufps $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * shufps $1, (%rax), %xmm2 +# CHECK-NEXT: 1 14 14.00 sqrtps %xmm0, %xmm2 +# CHECK-NEXT: 2 20 14.00 * sqrtps (%rax), %xmm2 +# CHECK-NEXT: 1 14 14.00 sqrtss %xmm0, %xmm2 +# CHECK-NEXT: 2 20 14.00 * sqrtss (%rax), %xmm2 +# CHECK-NEXT: 4 5 1.00 * * U stmxcsr (%rax) +# CHECK-NEXT: 1 3 1.00 subps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * subps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 subss %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * subss (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 ucomiss %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * ucomiss (%rax), %xmm1 +# CHECK-NEXT: 1 1 1.00 unpckhps %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * unpckhps (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 unpcklps %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * unpcklps (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 xorps %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * xorps (%rax), %xmm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - 112.00 41.00 55.50 10.00 34.50 33.50 33.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - addps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - addss %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addss (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - andnps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 andnps (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - andps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 andps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - cmpeqps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cmpeqps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - cmpeqss %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cmpeqss (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - comiss %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 comiss (%rax), %xmm1 +# CHECK-NEXT: - - - 1.00 - - - - cvtpi2ps %mm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtpi2ps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - cvtps2pi %xmm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtps2pi (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - cvtsi2ss %ecx, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - cvtsi2ss %rcx, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtsi2ssl (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtsi2ssl (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - cvtss2si %xmm0, %ecx +# CHECK-NEXT: - - 1.00 1.00 - - - - cvtss2si %xmm0, %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvtss2si (%rax), %ecx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvtss2si (%rax), %rcx +# CHECK-NEXT: - - - 1.00 - - - - cvttps2pi %xmm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvttps2pi (%rax), %mm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - cvttss2si %xmm0, %ecx +# CHECK-NEXT: - - 1.00 1.00 - - - - cvttss2si %xmm0, %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvttss2si (%rax), %ecx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvttss2si (%rax), %rcx +# CHECK-NEXT: - 14.00 1.00 - - - - - divps %xmm0, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 divps (%rax), %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - - - divss %xmm0, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 divss (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 ldmxcsr (%rax) +# CHECK-NEXT: - - - - - 1.00 - - maskmovq %mm0, %mm1 +# CHECK-NEXT: - - - 1.00 - - - - maxps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 maxps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - maxss %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 maxss (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - minps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 minps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - minss %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 minss (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movaps %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movaps %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movaps (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movhlps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movlhps %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movhps %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 movhps (%rax), %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movlps %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 movlps (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - movmskps %xmm0, %ecx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntps %xmm0, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntq %mm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 - - movss %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movss %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movss (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movups %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movups %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movups (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - mulps %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 mulps (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - mulss %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 mulss (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - orps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 orps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - pavgb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pavgb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pavgw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pavgw (%rax), %mm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrw $1, %mm0, %ecx +# CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrw $1, %eax, %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrw $1, (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pmaxsw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pmaxsw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pmaxub %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pmaxub (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pminsw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pminsw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pminub %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pminub (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmovmskb %mm0, %ecx +# CHECK-NEXT: - - 1.00 - - - - - pmulhuw %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhuw (%rax), %mm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetcht0 (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetcht1 (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetcht2 (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetchnta (%rax) +# CHECK-NEXT: - - 1.00 - - - - - psadbw %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 psadbw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - pshufw $1, %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 pshufw $1, (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - rcpps %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 rcpps (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - rcpss %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 rcpss (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - rsqrtps %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 rsqrtps (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - rsqrtss %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 rsqrtss (%rax), %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 sfence +# CHECK-NEXT: - - - - - 1.00 - - shufps $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 shufps $1, (%rax), %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - - - sqrtps %xmm0, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 sqrtps (%rax), %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - - - sqrtss %xmm0, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 sqrtss (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 stmxcsr (%rax) +# CHECK-NEXT: - - - 1.00 - - - - subps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 subps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - subss %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 subss (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - ucomiss %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 ucomiss (%rax), %xmm1 +# CHECK-NEXT: - - - - - 1.00 - - unpckhps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 unpckhps (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - unpcklps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 unpcklps (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - xorps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 xorps (%rax), %xmm2 diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s b/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s new file mode 100644 index 00000000000..4e720e42d7d --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s @@ -0,0 +1,960 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +addpd %xmm0, %xmm2 +addpd (%rax), %xmm2 + +addsd %xmm0, %xmm2 +addsd (%rax), %xmm2 + +andnpd %xmm0, %xmm2 +andnpd (%rax), %xmm2 + +andpd %xmm0, %xmm2 +andpd (%rax), %xmm2 + +clflush (%rax) + +cmppd $0, %xmm0, %xmm2 +cmppd $0, (%rax), %xmm2 + +cmpsd $0, %xmm0, %xmm2 +cmpsd $0, (%rax), %xmm2 + +comisd %xmm0, %xmm1 +comisd (%rax), %xmm1 + +cvtdq2pd %xmm0, %xmm2 +cvtdq2pd (%rax), %xmm2 + +cvtdq2ps %xmm0, %xmm2 +cvtdq2ps (%rax), %xmm2 + +cvtpd2dq %xmm0, %xmm2 +cvtpd2dq (%rax), %xmm2 + +cvtpd2pi %xmm0, %mm2 +cvtpd2pi (%rax), %mm2 + +cvtpd2ps %xmm0, %xmm2 +cvtpd2ps (%rax), %xmm2 + +cvtpi2pd %mm0, %xmm2 +cvtpi2pd (%rax), %xmm2 + +cvtps2dq %xmm0, %xmm2 +cvtps2dq (%rax), %xmm2 + +cvtps2pd %xmm0, %xmm2 +cvtps2pd (%rax), %xmm2 + +cvtsd2si %xmm0, %ecx +cvtsd2si %xmm0, %rcx +cvtsd2si (%rax), %ecx +cvtsd2si (%rax), %rcx + +cvtsd2ss %xmm0, %xmm2 +cvtsd2ss (%rax), %xmm2 + +cvtsi2sd %ecx, %xmm2 +cvtsi2sd %rcx, %xmm2 +cvtsi2sd (%rax), %xmm2 +cvtsi2sd (%rax), %xmm2 + +cvtss2sd %xmm0, %xmm2 +cvtss2sd (%rax), %xmm2 + +cvttpd2dq %xmm0, %xmm2 +cvttpd2dq (%rax), %xmm2 + +cvttpd2pi %xmm0, %mm2 +cvttpd2pi (%rax), %mm2 + +cvttps2dq %xmm0, %xmm2 +cvttps2dq (%rax), %xmm2 + +cvttsd2si %xmm0, %ecx +cvttsd2si %xmm0, %rcx +cvttsd2si (%rax), %ecx +cvttsd2si (%rax), %rcx + +divpd %xmm0, %xmm2 +divpd (%rax), %xmm2 + +divsd %xmm0, %xmm2 +divsd (%rax), %xmm2 + +lfence + +maskmovdqu %xmm0, %xmm1 + +maxpd %xmm0, %xmm2 +maxpd (%rax), %xmm2 + +maxsd %xmm0, %xmm2 +maxsd (%rax), %xmm2 + +mfence + +minpd %xmm0, %xmm2 +minpd (%rax), %xmm2 + +minsd %xmm0, %xmm2 +minsd (%rax), %xmm2 + +movapd %xmm0, %xmm2 +movapd %xmm0, (%rax) +movapd (%rax), %xmm2 + +movd %eax, %xmm2 +movd (%rax), %xmm2 + +movd %xmm0, %ecx +movd %xmm0, (%rax) + +movdqa %xmm0, %xmm2 +movdqa %xmm0, (%rax) +movdqa (%rax), %xmm2 + +movdqu %xmm0, %xmm2 +movdqu %xmm0, (%rax) +movdqu (%rax), %xmm2 + +movdq2q %xmm0, %mm2 + +movhpd %xmm0, (%rax) +movhpd (%rax), %xmm2 + +movlpd %xmm0, (%rax) +movlpd (%rax), %xmm2 + +movmskpd %xmm0, %rcx + +movntil %eax, (%rax) +movntiq %rax, (%rax) + +movntdq %xmm0, (%rax) +movntpd %xmm0, (%rax) + +movq %xmm0, %xmm2 + +movq %rax, %xmm2 +movq (%rax), %xmm2 + +movq %xmm0, %rcx +movq %xmm0, (%rax) + +movq2dq %mm0, %xmm2 + +movsd %xmm0, %xmm2 +movsd %xmm0, (%rax) +movsd (%rax), %xmm2 + +movupd %xmm0, %xmm2 +movupd %xmm0, (%rax) +movupd (%rax), %xmm2 + +mulpd %xmm0, %xmm2 +mulpd (%rax), %xmm2 + +mulsd %xmm0, %xmm2 +mulsd (%rax), %xmm2 + +orpd %xmm0, %xmm2 +orpd (%rax), %xmm2 + +packssdw %xmm0, %xmm2 +packssdw (%rax), %xmm2 + +packsswb %xmm0, %xmm2 +packsswb (%rax), %xmm2 + +packuswb %xmm0, %xmm2 +packuswb (%rax), %xmm2 + +paddb %xmm0, %xmm2 +paddb (%rax), %xmm2 + +paddd %xmm0, %xmm2 +paddd (%rax), %xmm2 + +paddq %mm0, %mm2 +paddq (%rax), %mm2 + +paddq %xmm0, %xmm2 +paddq (%rax), %xmm2 + +paddsb %xmm0, %xmm2 +paddsb (%rax), %xmm2 + +paddsw %xmm0, %xmm2 +paddsw (%rax), %xmm2 + +paddusb %xmm0, %xmm2 +paddusb (%rax), %xmm2 + +paddusw %xmm0, %xmm2 +paddusw (%rax), %xmm2 + +paddw %xmm0, %xmm2 +paddw (%rax), %xmm2 + +pand %xmm0, %xmm2 +pand (%rax), %xmm2 + +pandn %xmm0, %xmm2 +pandn (%rax), %xmm2 + +pavgb %xmm0, %xmm2 +pavgb (%rax), %xmm2 + +pavgw %xmm0, %xmm2 +pavgw (%rax), %xmm2 + +pcmpeqb %xmm0, %xmm2 +pcmpeqb (%rax), %xmm2 + +pcmpeqd %xmm0, %xmm2 +pcmpeqd (%rax), %xmm2 + +pcmpeqw %xmm0, %xmm2 +pcmpeqw (%rax), %xmm2 + +pcmpgtb %xmm0, %xmm2 +pcmpgtb (%rax), %xmm2 + +pcmpgtd %xmm0, %xmm2 +pcmpgtd (%rax), %xmm2 + +pcmpgtw %xmm0, %xmm2 +pcmpgtw (%rax), %xmm2 + +pextrw $1, %xmm0, %rcx + +pinsrw $1, %rax, %xmm0 +pinsrw $1, (%rax), %xmm0 + +pmaddwd %xmm0, %xmm2 +pmaddwd (%rax), %xmm2 + +pmaxsw %xmm0, %xmm2 +pmaxsw (%rax), %xmm2 + +pmaxub %xmm0, %xmm2 +pmaxub (%rax), %xmm2 + +pminsw %xmm0, %xmm2 +pminsw (%rax), %xmm2 + +pminub %xmm0, %xmm2 +pminub (%rax), %xmm2 + +pmovmskb %xmm0, %rcx + +pmulhuw %xmm0, %xmm2 +pmulhuw (%rax), %xmm2 + +pmulhw %xmm0, %xmm2 +pmulhw (%rax), %xmm2 + +pmullw %xmm0, %xmm2 +pmullw (%rax), %xmm2 + +pmuludq %mm0, %mm2 +pmuludq (%rax), %mm2 + +pmuludq %xmm0, %xmm2 +pmuludq (%rax), %xmm2 + +por %xmm0, %xmm2 +por (%rax), %xmm2 + +psadbw %xmm0, %xmm2 +psadbw (%rax), %xmm2 + +pshufd $1, %xmm0, %xmm2 +pshufd $1, (%rax), %xmm2 + +pshufhw $1, %xmm0, %xmm2 +pshufhw $1, (%rax), %xmm2 + +pshuflw $1, %xmm0, %xmm2 +pshuflw $1, (%rax), %xmm2 + +pslld $1, %xmm2 +pslld %xmm0, %xmm2 +pslld (%rax), %xmm2 + +pslldq $1, %xmm2 + +psllq $1, %xmm2 +psllq %xmm0, %xmm2 +psllq (%rax), %xmm2 + +psllw $1, %xmm2 +psllw %xmm0, %xmm2 +psllw (%rax), %xmm2 + +psrad $1, %xmm2 +psrad %xmm0, %xmm2 +psrad (%rax), %xmm2 + +psraw $1, %xmm2 +psraw %xmm0, %xmm2 +psraw (%rax), %xmm2 + +psrld $1, %xmm2 +psrld %xmm0, %xmm2 +psrld (%rax), %xmm2 + +psrldq $1, %xmm2 + +psrlq $1, %xmm2 +psrlq %xmm0, %xmm2 +psrlq (%rax), %xmm2 + +psrlw $1, %xmm2 +psrlw %xmm0, %xmm2 +psrlw (%rax), %xmm2 + +psubb %xmm0, %xmm2 +psubb (%rax), %xmm2 + +psubd %xmm0, %xmm2 +psubd (%rax), %xmm2 + +psubq %mm0, %mm2 +psubq (%rax), %mm2 + +psubq %xmm0, %xmm2 +psubq (%rax), %xmm2 + +psubsb %xmm0, %xmm2 +psubsb (%rax), %xmm2 + +psubsw %xmm0, %xmm2 +psubsw (%rax), %xmm2 + +psubusb %xmm0, %xmm2 +psubusb (%rax), %xmm2 + +psubusw %xmm0, %xmm2 +psubusw (%rax), %xmm2 + +psubw %xmm0, %xmm2 +psubw (%rax), %xmm2 + +punpckhbw %xmm0, %xmm2 +punpckhbw (%rax), %xmm2 + +punpckhdq %xmm0, %xmm2 +punpckhdq (%rax), %xmm2 + +punpckhqdq %xmm0, %xmm2 +punpckhqdq (%rax), %xmm2 + +punpckhwd %xmm0, %xmm2 +punpckhwd (%rax), %xmm2 + +punpcklbw %xmm0, %xmm2 +punpcklbw (%rax), %xmm2 + +punpckldq %xmm0, %xmm2 +punpckldq (%rax), %xmm2 + +punpcklqdq %xmm0, %xmm2 +punpcklqdq (%rax), %xmm2 + +punpcklwd %xmm0, %xmm2 +punpcklwd (%rax), %xmm2 + +pxor %xmm0, %xmm2 +pxor (%rax), %xmm2 + +shufpd $1, %xmm0, %xmm2 +shufpd $1, (%rax), %xmm2 + +sqrtpd %xmm0, %xmm2 +sqrtpd (%rax), %xmm2 + +sqrtsd %xmm0, %xmm2 +sqrtsd (%rax), %xmm2 + +subpd %xmm0, %xmm2 +subpd (%rax), %xmm2 + +subsd %xmm0, %xmm2 +subsd (%rax), %xmm2 + +ucomisd %xmm0, %xmm1 +ucomisd (%rax), %xmm1 + +unpckhpd %xmm0, %xmm2 +unpckhpd (%rax), %xmm2 + +unpcklpd %xmm0, %xmm2 +unpcklpd (%rax), %xmm2 + +xorpd %xmm0, %xmm2 +xorpd (%rax), %xmm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 addpd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * addpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 addsd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * addsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 andnpd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * andnpd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 andpd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * andpd (%rax), %xmm2 +# CHECK-NEXT: 4 5 1.00 * * U clflush (%rax) +# CHECK-NEXT: 1 3 1.00 cmpeqpd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cmpeqpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 cmpeqsd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cmpeqsd (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 comisd %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * comisd (%rax), %xmm1 +# CHECK-NEXT: 2 4 1.00 cvtdq2pd %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtdq2pd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 cvtdq2ps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cvtdq2ps (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 cvtpd2dq %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtpd2dq (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 cvtpd2pi %xmm0, %mm2 +# CHECK-NEXT: 3 10 1.00 * cvtpd2pi (%rax), %mm2 +# CHECK-NEXT: 2 4 1.00 cvtpd2ps %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtpd2ps (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 cvtpi2pd %mm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtpi2pd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 cvtps2dq %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cvtps2dq (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 cvtps2pd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * cvtps2pd (%rax), %xmm2 +# CHECK-NEXT: 2 5 1.00 cvtsd2si %xmm0, %ecx +# CHECK-NEXT: 2 5 1.00 cvtsd2si %xmm0, %rcx +# CHECK-NEXT: 3 9 1.00 * cvtsd2si (%rax), %ecx +# CHECK-NEXT: 3 9 1.00 * cvtsd2si (%rax), %rcx +# CHECK-NEXT: 2 4 1.00 cvtsd2ss %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtsd2ss (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 cvtsi2sd %ecx, %xmm2 +# CHECK-NEXT: 2 4 1.00 cvtsi2sd %rcx, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cvtsi2sdl (%rax), %xmm2 +# CHECK-NEXT: 2 9 1.00 * cvtsi2sdl (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 cvtss2sd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * cvtss2sd (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 cvttpd2dq %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvttpd2dq (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 cvttpd2pi %xmm0, %mm2 +# CHECK-NEXT: 3 10 1.00 * cvttpd2pi (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 cvttps2dq %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cvttps2dq (%rax), %xmm2 +# CHECK-NEXT: 2 5 1.00 cvttsd2si %xmm0, %ecx +# CHECK-NEXT: 2 5 1.00 cvttsd2si %xmm0, %rcx +# CHECK-NEXT: 3 9 1.00 * cvttsd2si (%rax), %ecx +# CHECK-NEXT: 3 9 1.00 * cvttsd2si (%rax), %rcx +# CHECK-NEXT: 1 22 22.00 divpd %xmm0, %xmm2 +# CHECK-NEXT: 2 28 22.00 * divpd (%rax), %xmm2 +# CHECK-NEXT: 1 22 22.00 divsd %xmm0, %xmm2 +# CHECK-NEXT: 2 28 22.00 * divsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 * * U lfence +# CHECK-NEXT: 1 1 1.00 * * U maskmovdqu %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 maxpd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * maxpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 maxsd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * maxsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 * * U mfence +# CHECK-NEXT: 1 3 1.00 minpd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * minpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 minsd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * minsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movapd %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movapd %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movapd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movd %eax, %xmm2 +# CHECK-NEXT: 1 6 0.50 * movd (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 movd %xmm0, %ecx +# CHECK-NEXT: 1 1 1.00 * movd %xmm0, (%rax) +# CHECK-NEXT: 1 1 0.33 movdqa %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movdqa %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movdqa (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.33 movdqu %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movdqu %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movdqu (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 movdq2q %xmm0, %mm2 +# CHECK-NEXT: 1 1 1.00 * movhpd %xmm0, (%rax) +# CHECK-NEXT: 2 7 1.00 * movhpd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 * movlpd %xmm0, (%rax) +# CHECK-NEXT: 2 7 1.00 * movlpd (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 movmskpd %xmm0, %ecx +# CHECK-NEXT: 1 1 1.00 * movntil %eax, (%rax) +# CHECK-NEXT: 1 1 1.00 * movntiq %rax, (%rax) +# CHECK-NEXT: 1 1 1.00 * movntdq %xmm0, (%rax) +# CHECK-NEXT: 1 1 1.00 * movntpd %xmm0, (%rax) +# CHECK-NEXT: 1 1 0.33 movq %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 movq %rax, %xmm2 +# CHECK-NEXT: 1 6 0.50 * movq (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 movq %xmm0, %rcx +# CHECK-NEXT: 1 1 1.00 * movq %xmm0, (%rax) +# CHECK-NEXT: 1 1 0.33 movq2dq %mm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 movsd %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movsd %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movupd %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movupd %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movupd (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 mulpd %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * mulpd (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 mulsd %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * mulsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 orpd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * orpd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 packssdw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * packssdw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 packsswb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * packsswb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 packuswb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * packuswb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddq %mm0, %mm2 +# CHECK-NEXT: 2 7 0.50 * paddq (%rax), %mm2 +# CHECK-NEXT: 1 1 0.50 paddq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddsb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddsb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddsw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddsw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddusb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddusb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddusw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddusw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.33 pand %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pand (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.33 pandn %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pandn (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pavgb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pavgb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pavgw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pavgw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpeqb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpeqd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpeqw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpgtb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpgtb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpgtd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpgtd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpgtw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpgtw (%rax), %xmm2 +# CHECK-NEXT: 2 3 1.00 pextrw $1, %xmm0, %ecx +# CHECK-NEXT: 2 2 1.00 pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: 2 7 0.50 * pinsrw $1, (%rax), %xmm0 +# CHECK-NEXT: 1 5 1.00 pmaddwd %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmaddwd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmaxsw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmaxsw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmaxub %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmaxub (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pminsw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pminsw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pminub %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pminub (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 pmovmskb %xmm0, %ecx +# CHECK-NEXT: 1 5 1.00 pmulhuw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmulhuw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmulhw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmulhw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmullw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmullw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmuludq %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmuludq (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmuludq %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmuludq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.33 por %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * por (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 psadbw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * psadbw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pshufd $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pshufd $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pshufhw $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pshufhw $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pshuflw $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pshuflw $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 pslld $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 pslld %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * pslld (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pslldq $1, %xmm2 +# CHECK-NEXT: 1 1 1.00 psllq $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psllq %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psllq (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 psllw $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psllw %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psllw (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 psrad $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psrad %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psrad (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 psraw $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psraw %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psraw (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 psrld $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psrld %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psrld (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psrldq $1, %xmm2 +# CHECK-NEXT: 1 1 1.00 psrlq $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psrlq %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psrlq (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 psrlw $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psrlw %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psrlw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 psubq %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubq (%rax), %mm2 +# CHECK-NEXT: 1 1 0.50 psubq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubsb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubsb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubsw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubsw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubusb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubusb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubusw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubusw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpckhbw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpckhbw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpckhdq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpckhdq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpckhqdq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpckhqdq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpckhwd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpckhwd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpcklbw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpcklbw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpckldq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpckldq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpcklqdq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpcklqdq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpcklwd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpcklwd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.33 pxor %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pxor (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 shufpd $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * shufpd $1, (%rax), %xmm2 +# CHECK-NEXT: 1 21 21.00 sqrtpd %xmm0, %xmm2 +# CHECK-NEXT: 2 27 21.00 * sqrtpd (%rax), %xmm2 +# CHECK-NEXT: 1 21 21.00 sqrtsd %xmm0, %xmm2 +# CHECK-NEXT: 2 27 21.00 * sqrtsd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 subpd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * subpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 subsd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * subsd (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 ucomisd %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * ucomisd (%rax), %xmm1 +# CHECK-NEXT: 1 1 1.00 unpckhpd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * unpckhpd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 unpcklpd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * unpcklpd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 xorpd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * xorpd (%rax), %xmm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - 172.00 75.83 118.33 17.00 100.83 67.00 67.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - addpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - addsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - andnpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 andnpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - andpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 andpd (%rax), %xmm2 +# CHECK-NEXT: - - 0.50 0.50 1.00 1.00 0.50 0.50 clflush (%rax) +# CHECK-NEXT: - - - 1.00 - - - - cmpeqpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cmpeqpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - cmpeqsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cmpeqsd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - comisd %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 comisd (%rax), %xmm1 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtdq2pd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtdq2pd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - cvtdq2ps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtdq2ps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtpd2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtpd2dq (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtpd2pi %xmm0, %mm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtpd2pi (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtpd2ps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtpd2ps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtpi2pd %mm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtpi2pd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - cvtps2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtps2dq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - cvtps2pd %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 cvtps2pd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - cvtsd2si %xmm0, %ecx +# CHECK-NEXT: - - 1.00 1.00 - - - - cvtsd2si %xmm0, %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvtsd2si (%rax), %ecx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvtsd2si (%rax), %rcx +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtsd2ss %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtsd2ss (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtsi2sd %ecx, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtsi2sd %rcx, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtsi2sdl (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtsi2sdl (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - cvtss2sd %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 cvtss2sd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvttpd2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvttpd2dq (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvttpd2pi %xmm0, %mm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvttpd2pi (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - cvttps2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvttps2dq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - cvttsd2si %xmm0, %ecx +# CHECK-NEXT: - - 1.00 1.00 - - - - cvttsd2si %xmm0, %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvttsd2si (%rax), %ecx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvttsd2si (%rax), %rcx +# CHECK-NEXT: - 22.00 1.00 - - - - - divpd %xmm0, %xmm2 +# CHECK-NEXT: - 22.00 1.00 - - - 0.50 0.50 divpd (%rax), %xmm2 +# CHECK-NEXT: - 22.00 1.00 - - - - - divsd %xmm0, %xmm2 +# CHECK-NEXT: - 22.00 1.00 - - - 0.50 0.50 divsd (%rax), %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 lfence +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 maskmovdqu %xmm0, %xmm1 +# CHECK-NEXT: - - - 1.00 - - - - maxpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 maxpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - maxsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 maxsd (%rax), %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 mfence +# CHECK-NEXT: - - - 1.00 - - - - minpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 minpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - minsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 minsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movapd %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movapd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movapd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movd %eax, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - movd %xmm0, %ecx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movd %xmm0, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movdqa %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movdqa %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movdqa (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movdqu %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movdqu %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movdqu (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 - - movdq2q %xmm0, %mm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movhpd %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 movhpd (%rax), %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movlpd %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 movlpd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - movmskpd %xmm0, %ecx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntil %eax, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntiq %rax, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntdq %xmm0, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntpd %xmm0, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movq %rax, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - movq %xmm0, %rcx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movq %xmm0, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq2dq %mm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movsd %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movsd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movupd %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movupd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movupd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - mulpd %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 mulpd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - mulsd %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 mulsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - orpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 orpd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - packssdw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 packssdw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - packsswb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 packsswb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - packuswb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 packuswb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddq %mm0, %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddq (%rax), %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddsb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddsb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddsw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddsw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddusb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddusb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddusw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddusw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddw (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pand %xmm0, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pand (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pandn %xmm0, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pandn (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pavgb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pavgb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pavgw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pavgw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpeqb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpeqb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpeqd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpeqd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpeqw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpeqw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpgtb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpgtb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpgtd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpgtd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpgtw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpgtw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrw $1, %xmm0, %ecx +# CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrw $1, (%rax), %xmm0 +# CHECK-NEXT: - - 1.00 - - - - - pmaddwd %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmaddwd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxsw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxsw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxub %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxub (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pminsw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminsw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pminub %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminub (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pmovmskb %xmm0, %ecx +# CHECK-NEXT: - - 1.00 - - - - - pmulhuw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhuw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pmulhw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pmullw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmullw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pmuludq %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmuludq (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmuludq %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmuludq (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - por %xmm0, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 por (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psadbw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 psadbw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pshufd $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pshufd $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pshufhw $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pshufhw $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pshuflw $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pshuflw $1, (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pslld $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pslld %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 pslld (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pslldq $1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psllq $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psllq %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psllq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psllw $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psllw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psllw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psrad $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psrad %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psrad (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psraw $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psraw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psraw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psrld $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psrld %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psrld (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psrldq $1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psrlq $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psrlq %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psrlq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psrlw $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psrlw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psrlw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - psubq %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubq (%rax), %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubsb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubsb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubsw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubsw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubusb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubusb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubusw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubusw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckhbw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckhbw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckhdq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckhdq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckhqdq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckhqdq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckhwd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckhwd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpcklbw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpcklbw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckldq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckldq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpcklqdq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpcklqdq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpcklwd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpcklwd (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pxor %xmm0, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pxor (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - shufpd $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 shufpd $1, (%rax), %xmm2 +# CHECK-NEXT: - 21.00 1.00 - - - - - sqrtpd %xmm0, %xmm2 +# CHECK-NEXT: - 21.00 1.00 - - - 0.50 0.50 sqrtpd (%rax), %xmm2 +# CHECK-NEXT: - 21.00 1.00 - - - - - sqrtsd %xmm0, %xmm2 +# CHECK-NEXT: - 21.00 1.00 - - - 0.50 0.50 sqrtsd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - subpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 subpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - subsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 subsd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - ucomisd %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 ucomisd (%rax), %xmm1 +# CHECK-NEXT: - - - - - 1.00 - - unpckhpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 unpckhpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - unpcklpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 unpcklpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - xorpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 xorpd (%rax), %xmm2 diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-sse3.s b/test/tools/llvm-mca/X86/Barcelona/resources-sse3.s new file mode 100644 index 00000000000..7b4c0a34f31 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-sse3.s @@ -0,0 +1,104 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +addsubpd %xmm0, %xmm2 +addsubpd (%rax), %xmm2 + +addsubps %xmm0, %xmm2 +addsubps (%rax), %xmm2 + +haddpd %xmm0, %xmm2 +haddpd (%rax), %xmm2 + +haddps %xmm0, %xmm2 +haddps (%rax), %xmm2 + +hsubpd %xmm0, %xmm2 +hsubpd (%rax), %xmm2 + +hsubps %xmm0, %xmm2 +hsubps (%rax), %xmm2 + +lddqu (%rax), %xmm2 + +monitor + +movddup %xmm0, %xmm2 +movddup (%rax), %xmm2 + +movshdup %xmm0, %xmm2 +movshdup (%rax), %xmm2 + +movsldup %xmm0, %xmm2 +movsldup (%rax), %xmm2 + +mwait + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 addsubpd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * addsubpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 addsubps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * addsubps (%rax), %xmm2 +# CHECK-NEXT: 3 5 2.00 haddpd %xmm0, %xmm2 +# CHECK-NEXT: 4 11 2.00 * haddpd (%rax), %xmm2 +# CHECK-NEXT: 3 5 2.00 haddps %xmm0, %xmm2 +# CHECK-NEXT: 4 11 2.00 * haddps (%rax), %xmm2 +# CHECK-NEXT: 3 5 2.00 hsubpd %xmm0, %xmm2 +# CHECK-NEXT: 4 11 2.00 * hsubpd (%rax), %xmm2 +# CHECK-NEXT: 3 5 2.00 hsubps %xmm0, %xmm2 +# CHECK-NEXT: 4 11 2.00 * hsubps (%rax), %xmm2 +# CHECK-NEXT: 1 6 0.50 * lddqu (%rax), %xmm2 +# CHECK-NEXT: 1 100 0.33 U monitor +# CHECK-NEXT: 1 1 1.00 movddup %xmm0, %xmm2 +# CHECK-NEXT: 1 6 0.50 * movddup (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movshdup %xmm0, %xmm2 +# CHECK-NEXT: 1 6 0.50 * movshdup (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movsldup %xmm0, %xmm2 +# CHECK-NEXT: 1 6 0.50 * movsldup (%rax), %xmm2 +# CHECK-NEXT: 1 100 0.33 * * U mwait + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 0.67 12.67 - 19.67 5.00 5.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - addsubpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addsubpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - addsubps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addsubps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - haddpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 haddpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - haddps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 haddps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - hsubpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 hsubpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - hsubps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 hsubps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 lddqu (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - monitor +# CHECK-NEXT: - - - - - 1.00 - - movddup %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movddup (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movshdup %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movshdup (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movsldup %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movsldup (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - mwait diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-sse4a.s b/test/tools/llvm-mca/X86/Barcelona/resources-sse4a.s new file mode 100644 index 00000000000..f4b9c94d48a --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-sse4a.s @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +extrq %xmm0, %xmm2 +extrq $22, $2, %xmm2 + +insertq %xmm0, %xmm2 +insertq $22, $22, %xmm0, %xmm2 + +movntsd %xmm0, (%rax) +movntss %xmm0, (%rax) + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.50 extrq %xmm0, %xmm2 +# CHECK-NEXT: 1 1 0.50 extrq $22, $2, %xmm2 +# CHECK-NEXT: 1 1 0.50 insertq %xmm0, %xmm2 +# CHECK-NEXT: 1 1 0.50 insertq $22, $22, %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movntsd %xmm0, (%rax) +# CHECK-NEXT: 1 1 1.00 * movntss %xmm0, (%rax) + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 2.00 2.00 2.00 1.00 1.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 0.50 - 0.50 - - extrq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - extrq $22, $2, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - insertq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - insertq $22, $22, %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntsd %xmm0, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntss %xmm0, (%rax) diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-x86_32.s b/test/tools/llvm-mca/X86/Barcelona/resources-x86_32.s new file mode 100644 index 00000000000..b4672620cf4 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-x86_32.s @@ -0,0 +1,78 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +aaa + +aad +aad $7 + +aam +aam $7 + +aas + +bound %bx, (%eax) +bound %ebx, (%eax) + +daa + +das + +into + +leave + +salc + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.33 aaa +# CHECK-NEXT: 1 100 0.33 aad +# CHECK-NEXT: 1 100 0.33 aad $7 +# CHECK-NEXT: 1 100 0.33 aam +# CHECK-NEXT: 1 100 0.33 aam $7 +# CHECK-NEXT: 1 100 0.33 aas +# CHECK-NEXT: 1 100 0.33 U bound %bx, (%eax) +# CHECK-NEXT: 1 100 0.33 U bound %ebx, (%eax) +# CHECK-NEXT: 1 100 0.33 daa +# CHECK-NEXT: 1 100 0.33 das +# CHECK-NEXT: 1 100 0.33 U into +# CHECK-NEXT: 3 7 0.67 * leave +# CHECK-NEXT: 1 1 0.33 U salc + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 4.67 4.67 - 4.67 0.50 0.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aaa +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aad +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aad $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aam +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aam $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aas +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - bound %bx, (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - bound %ebx, (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - daa +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - das +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - into +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 leave +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - salc diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s b/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s new file mode 100644 index 00000000000..194e257b645 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s @@ -0,0 +1,2476 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +adcb $0, %al +adcb $0, %dil +adcb $0, (%rax) +adcb $7, %al +adcb $7, %dil +adcb $7, (%rax) +adcb %sil, %dil +adcb %sil, (%rax) +adcb (%rax), %dil + +adcw $0, %ax +adcw $0, %di +adcw $0, (%rax) +adcw $511, %ax +adcw $511, %di +adcw $511, (%rax) +adcw $7, %di +adcw $7, (%rax) +adcw %si, %di +adcw %si, (%rax) +adcw (%rax), %di + +adcl $0, %eax +adcl $0, %edi +adcl $0, (%rax) +adcl $665536, %eax +adcl $665536, %edi +adcl $665536, (%rax) +adcl $7, %edi +adcl $7, (%rax) +adcl %esi, %edi +adcl %esi, (%rax) +adcl (%rax), %edi + +adcq $0, %rax +adcq $0, %rdi +adcq $0, (%rax) +adcq $665536, %rax +adcq $665536, %rdi +adcq $665536, (%rax) +adcq $7, %rdi +adcq $7, (%rax) +adcq %rsi, %rdi +adcq %rsi, (%rax) +adcq (%rax), %rdi + +addb $7, %al +addb $7, %dil +addb $7, (%rax) +addb %sil, %dil +addb %sil, (%rax) +addb (%rax), %dil + +addw $511, %ax +addw $511, %di +addw $511, (%rax) +addw $7, %di +addw $7, (%rax) +addw %si, %di +addw %si, (%rax) +addw (%rax), %di + +addl $665536, %eax +addl $665536, %edi +addl $665536, (%rax) +addl $7, %edi +addl $7, (%rax) +addl %esi, %edi +addl %esi, (%rax) +addl (%rax), %edi + +addq $665536, %rax +addq $665536, %rdi +addq $665536, (%rax) +addq $7, %rdi +addq $7, (%rax) +addq %rsi, %rdi +addq %rsi, (%rax) +addq (%rax), %rdi + +andb $7, %al +andb $7, %dil +andb $7, (%rax) +andb %sil, %dil +andb %sil, (%rax) +andb (%rax), %dil + +andw $511, %ax +andw $511, %di +andw $511, (%rax) +andw $7, %di +andw $7, (%rax) +andw %si, %di +andw %si, (%rax) +andw (%rax), %di + +andl $665536, %eax +andl $665536, %edi +andl $665536, (%rax) +andl $7, %edi +andl $7, (%rax) +andl %esi, %edi +andl %esi, (%rax) +andl (%rax), %edi + +andq $665536, %rax +andq $665536, %rdi +andq $665536, (%rax) +andq $7, %rdi +andq $7, (%rax) +andq %rsi, %rdi +andq %rsi, (%rax) +andq (%rax), %rdi + +bsfw %si, %di +bsrw %si, %di +bsfw (%rax), %di +bsrw (%rax), %di + +bsfl %esi, %edi +bsrl %esi, %edi +bsfl (%rax), %edi +bsrl (%rax), %edi + +bsfq %rsi, %rdi +bsrq %rsi, %rdi +bsfq (%rax), %rdi +bsrq (%rax), %rdi + +bswap %eax +bswap %rax + +btw %si, %di +btcw %si, %di +btrw %si, %di +btsw %si, %di +btw %si, (%rax) +btcw %si, (%rax) +btrw %si, (%rax) +btsw %si, (%rax) +btw $7, %di +btcw $7, %di +btrw $7, %di +btsw $7, %di +btw $7, (%rax) +btcw $7, (%rax) +btrw $7, (%rax) +btsw $7, (%rax) + +btl %esi, %edi +btcl %esi, %edi +btrl %esi, %edi +btsl %esi, %edi +btl %esi, (%rax) +btcl %esi, (%rax) +btrl %esi, (%rax) +btsl %esi, (%rax) +btl $7, %edi +btcl $7, %edi +btrl $7, %edi +btsl $7, %edi +btl $7, (%rax) +btcl $7, (%rax) +btrl $7, (%rax) +btsl $7, (%rax) + +btq %rsi, %rdi +btcq %rsi, %rdi +btrq %rsi, %rdi +btsq %rsi, %rdi +btq %rsi, (%rax) +btcq %rsi, (%rax) +btrq %rsi, (%rax) +btsq %rsi, (%rax) +btq $7, %rdi +btcq $7, %rdi +btrq $7, %rdi +btsq $7, %rdi +btq $7, (%rax) +btcq $7, (%rax) +btrq $7, (%rax) +btsq $7, (%rax) + +cbw +cwde +cdqe +cwd +cdq +cqo + +clc +cld +cmc + +cmpb $7, %al +cmpb $7, %dil +cmpb $7, (%rax) +cmpb %sil, %dil +cmpb %sil, (%rax) +cmpb (%rax), %dil + +cmpw $511, %ax +cmpw $511, %di +cmpw $511, (%rax) +cmpw $7, %di +cmpw $7, (%rax) +cmpw %si, %di +cmpw %si, (%rax) +cmpw (%rax), %di + +cmpl $665536, %eax +cmpl $665536, %edi +cmpl $665536, (%rax) +cmpl $7, %edi +cmpl $7, (%rax) +cmpl %esi, %edi +cmpl %esi, (%rax) +cmpl (%rax), %edi + +cmpq $665536, %rax +cmpq $665536, %rdi +cmpq $665536, (%rax) +cmpq $7, %rdi +cmpq $7, (%rax) +cmpq %rsi, %rdi +cmpq %rsi, (%rax) +cmpq (%rax), %rdi + +cmpsb +cmpsw +cmpsl +cmpsq + +cmpxchgb %cl, %bl +cmpxchgb %cl, (%rbx) + +cmpxchgw %cx, %bx +cmpxchgw %cx, (%rbx) + +cmpxchgl %ecx, %ebx +cmpxchgl %ecx, (%rbx) + +cmpxchgq %rcx, %rbx +cmpxchgq %rcx, (%rbx) + +cpuid + +decb %dil +decb (%rax) +decw %di +decw (%rax) +decl %edi +decl (%rax) +decq %rdi +decq (%rax) + +divb %dil +divb (%rax) +divw %si +divw (%rax) +divl %edx +divl (%rax) +divq %rcx +divq (%rax) + +enter $7, $4095 + +idivb %dil +idivb (%rax) +idivw %si +idivw (%rax) +idivl %edx +idivl (%rax) +idivq %rcx +idivq (%rax) + +imulb %dil +imulb (%rax) + +imulw %di +imulw (%rax) +imulw %si, %di +imulw (%rax), %di +imulw $511, %si, %di +imulw $511, (%rax), %di +imulw $7, %si, %di +imulw $7, (%rax), %di + +imull %edi +imull (%rax) +imull %esi, %edi +imull (%rax), %edi +imull $665536, %esi, %edi +imull $665536, (%rax), %edi +imull $7, %esi, %edi +imull $7, (%rax), %edi + +imulq %rdi +imulq (%rax) +imulq %rsi, %rdi +imulq (%rax), %rdi +imulq $665536, %rsi, %rdi +imulq $665536, (%rax), %rdi +imulq $7, %rsi, %rdi +imulq $7, (%rax), %rdi + +inb $7, %al +inb %dx, %al +inw $7, %ax +inw %dx, %ax +inl $7, %eax +inl %dx, %eax + +incb %dil +incb (%rax) +incw %di +incw (%rax) +incl %edi +incl (%rax) +incq %rdi +incq (%rax) + +insb +insw +insl + +int $7 + +invlpg (%rax) +invlpga %rax, %ecx + +lahf + +leave + +lodsb +lodsw +lodsl +lodsq + +movsb +movsw +movsl +movsq + +movsbw %al, %di +movzbw %al, %di +movsbw (%rax), %di +movzbw (%rax), %di +movsbl %al, %edi +movzbl %al, %edi +movsbl (%rax), %edi +movzbl (%rax), %edi +movsbq %al, %rdi +movzbq %al, %rdi +movsbq (%rax), %rdi +movzbq (%rax), %rdi + +movswl %ax, %edi +movzwl %ax, %edi +movswl (%rax), %edi +movzwl (%rax), %edi +movswq %ax, %rdi +movzwq %ax, %rdi +movswq (%rax), %rdi +movzwq (%rax), %rdi + +movslq %eax, %rdi +movslq (%rax), %rdi + +mulb %dil +mulb (%rax) +mulw %si +mulw (%rax) +mull %edx +mull (%rax) +mulq %rcx +mulq (%rax) + +negb %dil +negb (%r8) +negw %si +negw (%r9) +negl %edx +negl (%rax) +negq %rcx +negq (%r10) + +nop +nopw %di +nopw (%rcx) +nopl %esi +nopl (%r8) +nopq %rdx +nopq (%r9) + +notb %dil +notb (%r8) +notw %si +notw (%r9) +notl %edx +notl (%rax) +notq %rcx +notq (%r10) + +orb $7, %al +orb $7, %dil +orb $7, (%rax) +orb %sil, %dil +orb %sil, (%rax) +orb (%rax), %dil + +orw $511, %ax +orw $511, %di +orw $511, (%rax) +orw $7, %di +orw $7, (%rax) +orw %si, %di +orw %si, (%rax) +orw (%rax), %di + +orl $665536, %eax +orl $665536, %edi +orl $665536, (%rax) +orl $7, %edi +orl $7, (%rax) +orl %esi, %edi +orl %esi, (%rax) +orl (%rax), %edi + +orq $665536, %rax +orq $665536, %rdi +orq $665536, (%rax) +orq $7, %rdi +orq $7, (%rax) +orq %rsi, %rdi +orq %rsi, (%rax) +orq (%rax), %rdi + +outb %al, $7 +outb %al, %dx +outw %ax, $7 +outw %ax, %dx +outl %eax, $7 +outl %eax, %dx + +outsb +outsw +outsl + +pause + +rclb %dil +rcrb %dil +rclb (%rax) +rcrb (%rax) +rclb $7, %dil +rcrb $7, %dil +rclb $7, (%rax) +rcrb $7, (%rax) +rclb %cl, %dil +rcrb %cl, %dil +rclb %cl, (%rax) +rcrb %cl, (%rax) + +rclw %di +rcrw %di +rclw (%rax) +rcrw (%rax) +rclw $7, %di +rcrw $7, %di +rclw $7, (%rax) +rcrw $7, (%rax) +rclw %cl, %di +rcrw %cl, %di +rclw %cl, (%rax) +rcrw %cl, (%rax) + +rcll %edi +rcrl %edi +rcll (%rax) +rcrl (%rax) +rcll $7, %edi +rcrl $7, %edi +rcll $7, (%rax) +rcrl $7, (%rax) +rcll %cl, %edi +rcrl %cl, %edi +rcll %cl, (%rax) +rcrl %cl, (%rax) + +rclq %rdi +rcrq %rdi +rclq (%rax) +rcrq (%rax) +rclq $7, %rdi +rcrq $7, %rdi +rclq $7, (%rax) +rcrq $7, (%rax) +rclq %cl, %rdi +rcrq %cl, %rdi +rclq %cl, (%rax) +rcrq %cl, (%rax) + +rdmsr +rdpmc +rdtsc +rdtscp + +rolb %dil +rorb %dil +rolb (%rax) +rorb (%rax) +rolb $7, %dil +rorb $7, %dil +rolb $7, (%rax) +rorb $7, (%rax) +rolb %cl, %dil +rorb %cl, %dil +rolb %cl, (%rax) +rorb %cl, (%rax) + +rolw %di +rorw %di +rolw (%rax) +rorw (%rax) +rolw $7, %di +rorw $7, %di +rolw $7, (%rax) +rorw $7, (%rax) +rolw %cl, %di +rorw %cl, %di +rolw %cl, (%rax) +rorw %cl, (%rax) + +roll %edi +rorl %edi +roll (%rax) +rorl (%rax) +roll $7, %edi +rorl $7, %edi +roll $7, (%rax) +rorl $7, (%rax) +roll %cl, %edi +rorl %cl, %edi +roll %cl, (%rax) +rorl %cl, (%rax) + +rolq %rdi +rorq %rdi +rolq (%rax) +rorq (%rax) +rolq $7, %rdi +rorq $7, %rdi +rolq $7, (%rax) +rorq $7, (%rax) +rolq %cl, %rdi +rorq %cl, %rdi +rolq %cl, (%rax) +rorq %cl, (%rax) + +sahf + +sarb %dil +shlb %dil +shrb %dil +sarb (%rax) +shlb (%rax) +shrb (%rax) +sarb $7, %dil +shlb $7, %dil +shrb $7, %dil +sarb $7, (%rax) +shlb $7, (%rax) +shrb $7, (%rax) +sarb %cl, %dil +shlb %cl, %dil +shrb %cl, %dil +sarb %cl, (%rax) +shlb %cl, (%rax) +shrb %cl, (%rax) + +sarw %di +shlw %di +shrw %di +sarw (%rax) +shlw (%rax) +shrw (%rax) +sarw $7, %di +shlw $7, %di +shrw $7, %di +sarw $7, (%rax) +shlw $7, (%rax) +shrw $7, (%rax) +sarw %cl, %di +shlw %cl, %di +shrw %cl, %di +sarw %cl, (%rax) +shlw %cl, (%rax) +shrw %cl, (%rax) + +sarl %edi +shll %edi +shrl %edi +sarl (%rax) +shll (%rax) +shrl (%rax) +sarl $7, %edi +shll $7, %edi +shrl $7, %edi +sarl $7, (%rax) +shll $7, (%rax) +shrl $7, (%rax) +sarl %cl, %edi +shll %cl, %edi +shrl %cl, %edi +sarl %cl, (%rax) +shll %cl, (%rax) +shrl %cl, (%rax) + +sarq %rdi +shlq %rdi +shrq %rdi +sarq (%rax) +shlq (%rax) +shrq (%rax) +sarq $7, %rdi +shlq $7, %rdi +shrq $7, %rdi +sarq $7, (%rax) +shlq $7, (%rax) +shrq $7, (%rax) +sarq %cl, %rdi +shlq %cl, %rdi +shrq %cl, %rdi +sarq %cl, (%rax) +shlq %cl, (%rax) +shrq %cl, (%rax) + +sbbb $0, %al +sbbb $0, %dil +sbbb $0, (%rax) +sbbb $7, %al +sbbb $7, %dil +sbbb $7, (%rax) +sbbb %sil, %dil +sbbb %sil, (%rax) +sbbb (%rax), %dil + +sbbw $0, %ax +sbbw $0, %di +sbbw $0, (%rax) +sbbw $511, %ax +sbbw $511, %di +sbbw $511, (%rax) +sbbw $7, %di +sbbw $7, (%rax) +sbbw %si, %di +sbbw %si, (%rax) +sbbw (%rax), %di + +sbbl $0, %eax +sbbl $0, %edi +sbbl $0, (%rax) +sbbl $665536, %eax +sbbl $665536, %edi +sbbl $665536, (%rax) +sbbl $7, %edi +sbbl $7, (%rax) +sbbl %esi, %edi +sbbl %esi, (%rax) +sbbl (%rax), %edi + +sbbq $0, %rax +sbbq $0, %rdi +sbbq $0, (%rax) +sbbq $665536, %rax +sbbq $665536, %rdi +sbbq $665536, (%rax) +sbbq $7, %rdi +sbbq $7, (%rax) +sbbq %rsi, %rdi +sbbq %rsi, (%rax) +sbbq (%rax), %rdi + +scasb +scasw +scasl +scasq + +seto %al +seto (%rax) +setno %al +setno (%rax) +setb %al +setb (%rax) +setnb %al +setnb (%rax) +setz %al +setz (%rax) +setnz %al +setnz (%rax) +seta %al +seta (%rax) +setna %al +setna (%rax) +sets %al +sets (%rax) +setns %al +setns (%rax) +setp %al +setp (%rax) +setnp %al +setnp (%rax) +setl %al +setl (%rax) +setnl %al +setnl (%rax) +setg %al +setg (%rax) +setng %al +setng (%rax) + +shldw %cl, %si, %di +shrdw %cl, %si, %di +shldw %cl, %si, (%rax) +shrdw %cl, %si, (%rax) +shldw $7, %si, %di +shrdw $7, %si, %di +shldw $7, %si, (%rax) +shrdw $7, %si, (%rax) + +shldl %cl, %esi, %edi +shrdl %cl, %esi, %edi +shldl %cl, %esi, (%rax) +shrdl %cl, %esi, (%rax) +shldl $7, %esi, %edi +shrdl $7, %esi, %edi +shldl $7, %esi, (%rax) +shrdl $7, %esi, (%rax) + +shldq %cl, %rsi, %rdi +shrdq %cl, %rsi, %rdi +shldq %cl, %rsi, (%rax) +shrdq %cl, %rsi, (%rax) +shldq $7, %rsi, %rdi +shrdq $7, %rsi, %rdi +shldq $7, %rsi, (%rax) +shrdq $7, %rsi, (%rax) + +stc +std + +stosb +stosw +stosl +stosq + +subb $7, %al +subb $7, %dil +subb $7, (%rax) +subb %sil, %dil +subb %sil, (%rax) +subb (%rax), %dil + +subw $511, %ax +subw $511, %di +subw $511, (%rax) +subw $7, %di +subw $7, (%rax) +subw %si, %di +subw %si, (%rax) +subw (%rax), %di + +subl $665536, %eax +subl $665536, %edi +subl $665536, (%rax) +subl $7, %edi +subl $7, (%rax) +subl %esi, %edi +subl %esi, (%rax) +subl (%rax), %edi + +subq $665536, %rax +subq $665536, %rdi +subq $665536, (%rax) +subq $7, %rdi +subq $7, (%rax) +subq %rsi, %rdi +subq %rsi, (%rax) +subq (%rax), %rdi + +testb $7, %al +testb $7, %dil +testb $7, (%rax) +testb %sil, %dil +testb %sil, (%rax) + +testw $511, %ax +testw $511, %di +testw $511, (%rax) +testw $7, %di +testw $7, (%rax) +testw %si, %di +testw %si, (%rax) + +testl $665536, %eax +testl $665536, %edi +testl $665536, (%rax) +testl $7, %edi +testl $7, (%rax) +testl %esi, %edi +testl %esi, (%rax) + +testq $665536, %rax +testq $665536, %rdi +testq $665536, (%rax) +testq $7, %rdi +testq $7, (%rax) +testq %rsi, %rdi +testq %rsi, (%rax) + +ud2 + +wrmsr + +xaddb %bl, %cl +xaddb %bl, (%rcx) + +xaddw %bx, %cx +xaddw %ax, (%rbx) + +xaddl %ebx, %ecx +xaddl %eax, (%rbx) + +xaddq %rbx, %rcx +xaddq %rax, (%rbx) + +xchgb %bl, %cl +xchgb %bl, (%rbx) + +xchgw %ax, %bx +xchgw %bx, %cx +xchgw %ax, (%rbx) + +xchgl %eax, %ebx +xchgl %ebx, %ecx +xchgl %eax, (%rbx) + +xchgq %rax, %rbx +xchgq %rbx, %rcx +xchgq %rax, (%rbx) + +xlatb + +xorb $7, %al +xorb $7, %dil +xorb $7, (%rax) +xorb %sil, %dil +xorb %sil, (%rax) +xorb (%rax), %dil + +xorw $511, %ax +xorw $511, %di +xorw $511, (%rax) +xorw $7, %di +xorw $7, (%rax) +xorw %si, %di +xorw %si, (%rax) +xorw (%rax), %di + +xorl $665536, %eax +xorl $665536, %edi +xorl $665536, (%rax) +xorl $7, %edi +xorl $7, (%rax) +xorl %esi, %edi +xorl %esi, (%rax) +xorl (%rax), %edi + +xorq $665536, %rax +xorq $665536, %rdi +xorq $665536, (%rax) +xorq $7, %rdi +xorq $7, (%rax) +xorq %rsi, %rdi +xorq %rsi, (%rax) +xorq (%rax), %rdi + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 2 0.67 adcb $0, %al +# CHECK-NEXT: 2 2 0.67 adcb $0, %dil +# CHECK-NEXT: 6 9 1.00 * * adcb $0, (%rax) +# CHECK-NEXT: 2 2 0.67 adcb $7, %al +# CHECK-NEXT: 2 2 0.67 adcb $7, %dil +# CHECK-NEXT: 6 9 1.00 * * adcb $7, (%rax) +# CHECK-NEXT: 2 2 0.67 adcb %sil, %dil +# CHECK-NEXT: 6 9 1.00 * * adcb %sil, (%rax) +# CHECK-NEXT: 3 7 0.67 * adcb (%rax), %dil +# CHECK-NEXT: 2 2 0.67 adcw $0, %ax +# CHECK-NEXT: 2 2 0.67 adcw $0, %di +# CHECK-NEXT: 6 9 1.00 * * adcw $0, (%rax) +# CHECK-NEXT: 2 2 0.67 adcw $511, %ax +# CHECK-NEXT: 2 2 0.67 adcw $511, %di +# CHECK-NEXT: 6 9 1.00 * * adcw $511, (%rax) +# CHECK-NEXT: 2 2 0.67 adcw $7, %di +# CHECK-NEXT: 6 9 1.00 * * adcw $7, (%rax) +# CHECK-NEXT: 2 2 0.67 adcw %si, %di +# CHECK-NEXT: 6 9 1.00 * * adcw %si, (%rax) +# CHECK-NEXT: 3 7 0.67 * adcw (%rax), %di +# CHECK-NEXT: 2 2 0.67 adcl $0, %eax +# CHECK-NEXT: 2 2 0.67 adcl $0, %edi +# CHECK-NEXT: 6 9 1.00 * * adcl $0, (%rax) +# CHECK-NEXT: 2 2 0.67 adcl $665536, %eax +# CHECK-NEXT: 2 2 0.67 adcl $665536, %edi +# CHECK-NEXT: 6 9 1.00 * * adcl $665536, (%rax) +# CHECK-NEXT: 2 2 0.67 adcl $7, %edi +# CHECK-NEXT: 6 9 1.00 * * adcl $7, (%rax) +# CHECK-NEXT: 2 2 0.67 adcl %esi, %edi +# CHECK-NEXT: 6 9 1.00 * * adcl %esi, (%rax) +# CHECK-NEXT: 3 7 0.67 * adcl (%rax), %edi +# CHECK-NEXT: 2 2 0.67 adcq $0, %rax +# CHECK-NEXT: 2 2 0.67 adcq $0, %rdi +# CHECK-NEXT: 6 9 1.00 * * adcq $0, (%rax) +# CHECK-NEXT: 2 2 0.67 adcq $665536, %rax +# CHECK-NEXT: 2 2 0.67 adcq $665536, %rdi +# CHECK-NEXT: 6 9 1.00 * * adcq $665536, (%rax) +# CHECK-NEXT: 2 2 0.67 adcq $7, %rdi +# CHECK-NEXT: 6 9 1.00 * * adcq $7, (%rax) +# CHECK-NEXT: 2 2 0.67 adcq %rsi, %rdi +# CHECK-NEXT: 6 9 1.00 * * adcq %rsi, (%rax) +# CHECK-NEXT: 3 7 0.67 * adcq (%rax), %rdi +# CHECK-NEXT: 1 1 0.33 addb $7, %al +# CHECK-NEXT: 1 1 0.33 addb $7, %dil +# CHECK-NEXT: 3 7 1.00 * * addb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 addb %sil, %dil +# CHECK-NEXT: 3 7 1.00 * * addb %sil, (%rax) +# CHECK-NEXT: 2 6 0.50 * addb (%rax), %dil +# CHECK-NEXT: 1 1 0.33 addw $511, %ax +# CHECK-NEXT: 1 1 0.33 addw $511, %di +# CHECK-NEXT: 3 7 1.00 * * addw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 addw $7, %di +# CHECK-NEXT: 3 7 1.00 * * addw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 addw %si, %di +# CHECK-NEXT: 3 7 1.00 * * addw %si, (%rax) +# CHECK-NEXT: 2 6 0.50 * addw (%rax), %di +# CHECK-NEXT: 1 1 0.33 addl $665536, %eax +# CHECK-NEXT: 1 1 0.33 addl $665536, %edi +# CHECK-NEXT: 3 7 1.00 * * addl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 addl $7, %edi +# CHECK-NEXT: 3 7 1.00 * * addl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 addl %esi, %edi +# CHECK-NEXT: 3 7 1.00 * * addl %esi, (%rax) +# CHECK-NEXT: 2 6 0.50 * addl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 addq $665536, %rax +# CHECK-NEXT: 1 1 0.33 addq $665536, %rdi +# CHECK-NEXT: 3 7 1.00 * * addq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 addq $7, %rdi +# CHECK-NEXT: 3 7 1.00 * * addq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 addq %rsi, %rdi +# CHECK-NEXT: 3 7 1.00 * * addq %rsi, (%rax) +# CHECK-NEXT: 2 6 0.50 * addq (%rax), %rdi +# CHECK-NEXT: 1 1 0.33 andb $7, %al +# CHECK-NEXT: 1 1 0.33 andb $7, %dil +# CHECK-NEXT: 3 7 1.00 * * andb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 andb %sil, %dil +# CHECK-NEXT: 3 7 1.00 * * andb %sil, (%rax) +# CHECK-NEXT: 2 6 0.50 * andb (%rax), %dil +# CHECK-NEXT: 1 1 0.33 andw $511, %ax +# CHECK-NEXT: 1 1 0.33 andw $511, %di +# CHECK-NEXT: 3 7 1.00 * * andw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 andw $7, %di +# CHECK-NEXT: 3 7 1.00 * * andw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 andw %si, %di +# CHECK-NEXT: 3 7 1.00 * * andw %si, (%rax) +# CHECK-NEXT: 2 6 0.50 * andw (%rax), %di +# CHECK-NEXT: 1 1 0.33 andl $665536, %eax +# CHECK-NEXT: 1 1 0.33 andl $665536, %edi +# CHECK-NEXT: 3 7 1.00 * * andl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 andl $7, %edi +# CHECK-NEXT: 3 7 1.00 * * andl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 andl %esi, %edi +# CHECK-NEXT: 3 7 1.00 * * andl %esi, (%rax) +# CHECK-NEXT: 2 6 0.50 * andl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 andq $665536, %rax +# CHECK-NEXT: 1 1 0.33 andq $665536, %rdi +# CHECK-NEXT: 3 7 1.00 * * andq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 andq $7, %rdi +# CHECK-NEXT: 3 7 1.00 * * andq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 andq %rsi, %rdi +# CHECK-NEXT: 3 7 1.00 * * andq %rsi, (%rax) +# CHECK-NEXT: 2 6 0.50 * andq (%rax), %rdi +# CHECK-NEXT: 1 3 1.00 bsfw %si, %di +# CHECK-NEXT: 1 3 1.00 bsrw %si, %di +# CHECK-NEXT: 2 8 1.00 * bsfw (%rax), %di +# CHECK-NEXT: 2 8 1.00 * bsrw (%rax), %di +# CHECK-NEXT: 1 3 1.00 bsfl %esi, %edi +# CHECK-NEXT: 1 3 1.00 bsrl %esi, %edi +# CHECK-NEXT: 2 8 1.00 * bsfl (%rax), %edi +# CHECK-NEXT: 2 8 1.00 * bsrl (%rax), %edi +# CHECK-NEXT: 1 3 1.00 bsfq %rsi, %rdi +# CHECK-NEXT: 1 3 1.00 bsrq %rsi, %rdi +# CHECK-NEXT: 2 8 1.00 * bsfq (%rax), %rdi +# CHECK-NEXT: 2 8 1.00 * bsrq (%rax), %rdi +# CHECK-NEXT: 1 1 1.00 bswapl %eax +# CHECK-NEXT: 2 2 1.00 bswapq %rax +# CHECK-NEXT: 1 1 0.50 btw %si, %di +# CHECK-NEXT: 1 1 0.50 btcw %si, %di +# CHECK-NEXT: 1 1 0.50 btrw %si, %di +# CHECK-NEXT: 1 1 0.50 btsw %si, %di +# CHECK-NEXT: 6 9 1.00 * btw %si, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btcw %si, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btrw %si, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btsw %si, (%rax) +# CHECK-NEXT: 1 1 0.50 btw $7, %di +# CHECK-NEXT: 1 1 0.50 btcw $7, %di +# CHECK-NEXT: 1 1 0.50 btrw $7, %di +# CHECK-NEXT: 1 1 0.50 btsw $7, %di +# CHECK-NEXT: 2 6 0.50 * btw $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btcw $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btrw $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btsw $7, (%rax) +# CHECK-NEXT: 1 1 0.50 btl %esi, %edi +# CHECK-NEXT: 1 1 0.50 btcl %esi, %edi +# CHECK-NEXT: 1 1 0.50 btrl %esi, %edi +# CHECK-NEXT: 1 1 0.50 btsl %esi, %edi +# CHECK-NEXT: 6 9 1.00 * btl %esi, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btcl %esi, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btrl %esi, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btsl %esi, (%rax) +# CHECK-NEXT: 1 1 0.50 btl $7, %edi +# CHECK-NEXT: 1 1 0.50 btcl $7, %edi +# CHECK-NEXT: 1 1 0.50 btrl $7, %edi +# CHECK-NEXT: 1 1 0.50 btsl $7, %edi +# CHECK-NEXT: 2 6 0.50 * btl $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btcl $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btrl $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btsl $7, (%rax) +# CHECK-NEXT: 1 1 0.50 btq %rsi, %rdi +# CHECK-NEXT: 1 1 0.50 btcq %rsi, %rdi +# CHECK-NEXT: 1 1 0.50 btrq %rsi, %rdi +# CHECK-NEXT: 1 1 0.50 btsq %rsi, %rdi +# CHECK-NEXT: 6 9 1.00 * btq %rsi, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btcq %rsi, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btrq %rsi, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btsq %rsi, (%rax) +# CHECK-NEXT: 1 1 0.50 btq $7, %rdi +# CHECK-NEXT: 1 1 0.50 btcq $7, %rdi +# CHECK-NEXT: 1 1 0.50 btrq $7, %rdi +# CHECK-NEXT: 1 1 0.50 btsq $7, %rdi +# CHECK-NEXT: 2 6 0.50 * btq $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btcq $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btrq $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btsq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 cbtw +# CHECK-NEXT: 1 1 0.33 cwtl +# CHECK-NEXT: 1 1 0.33 cltq +# CHECK-NEXT: 2 2 1.00 cwtd +# CHECK-NEXT: 1 1 0.50 cltd +# CHECK-NEXT: 1 1 0.50 cqto +# CHECK-NEXT: 1 1 0.25 U clc +# CHECK-NEXT: 1 1 0.33 U cld +# CHECK-NEXT: 1 1 0.33 U cmc +# CHECK-NEXT: 1 1 0.33 cmpb $7, %al +# CHECK-NEXT: 1 1 0.33 cmpb $7, %dil +# CHECK-NEXT: 2 6 0.50 * cmpb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpb %sil, %dil +# CHECK-NEXT: 2 6 0.50 * cmpb %sil, (%rax) +# CHECK-NEXT: 2 6 0.50 * cmpb (%rax), %dil +# CHECK-NEXT: 1 1 0.33 cmpw $511, %ax +# CHECK-NEXT: 1 1 0.33 cmpw $511, %di +# CHECK-NEXT: 2 6 0.50 * cmpw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpw $7, %di +# CHECK-NEXT: 2 6 0.50 * cmpw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpw %si, %di +# CHECK-NEXT: 2 6 0.50 * cmpw %si, (%rax) +# CHECK-NEXT: 2 6 0.50 * cmpw (%rax), %di +# CHECK-NEXT: 1 1 0.33 cmpl $665536, %eax +# CHECK-NEXT: 1 1 0.33 cmpl $665536, %edi +# CHECK-NEXT: 2 6 0.50 * cmpl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpl $7, %edi +# CHECK-NEXT: 2 6 0.50 * cmpl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpl %esi, %edi +# CHECK-NEXT: 2 6 0.50 * cmpl %esi, (%rax) +# CHECK-NEXT: 2 6 0.50 * cmpl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 cmpq $665536, %rax +# CHECK-NEXT: 1 1 0.33 cmpq $665536, %rdi +# CHECK-NEXT: 2 6 0.50 * cmpq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpq $7, %rdi +# CHECK-NEXT: 2 6 0.50 * cmpq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpq %rsi, %rdi +# CHECK-NEXT: 2 6 0.50 * cmpq %rsi, (%rax) +# CHECK-NEXT: 2 6 0.50 * cmpq (%rax), %rdi +# CHECK-NEXT: 5 8 1.00 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 8 1.00 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 8 1.00 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 8 1.00 U cmpsq %es:(%rdi), (%rsi) +# CHECK-NEXT: 4 5 1.33 cmpxchgb %cl, %bl +# CHECK-NEXT: 6 8 2.00 * * cmpxchgb %cl, (%rbx) +# CHECK-NEXT: 4 5 1.33 cmpxchgw %cx, %bx +# CHECK-NEXT: 6 8 2.00 * * cmpxchgw %cx, (%rbx) +# CHECK-NEXT: 4 5 1.33 cmpxchgl %ecx, %ebx +# CHECK-NEXT: 6 8 2.00 * * cmpxchgl %ecx, (%rbx) +# CHECK-NEXT: 4 5 1.33 cmpxchgq %rcx, %rbx +# CHECK-NEXT: 6 8 2.00 * * cmpxchgq %rcx, (%rbx) +# CHECK-NEXT: 1 100 0.33 U cpuid +# CHECK-NEXT: 1 1 0.33 decb %dil +# CHECK-NEXT: 3 7 1.00 * * decb (%rax) +# CHECK-NEXT: 1 1 0.33 decw %di +# CHECK-NEXT: 3 7 1.00 * * decw (%rax) +# CHECK-NEXT: 1 1 0.33 decl %edi +# CHECK-NEXT: 3 7 1.00 * * decl (%rax) +# CHECK-NEXT: 1 1 0.33 decq %rdi +# CHECK-NEXT: 3 7 1.00 * * decq (%rax) +# CHECK-NEXT: 1 25 10.00 U divb %dil +# CHECK-NEXT: 2 30 10.00 * U divb (%rax) +# CHECK-NEXT: 1 25 10.00 U divw %si +# CHECK-NEXT: 2 30 10.00 * U divw (%rax) +# CHECK-NEXT: 1 25 10.00 U divl %edx +# CHECK-NEXT: 2 30 10.00 * U divl (%rax) +# CHECK-NEXT: 1 25 10.00 U divq %rcx +# CHECK-NEXT: 2 30 10.00 * U divq (%rax) +# CHECK-NEXT: 1 100 0.33 U enter $7, $4095 +# CHECK-NEXT: 1 25 10.00 U idivb %dil +# CHECK-NEXT: 2 30 10.00 * U idivb (%rax) +# CHECK-NEXT: 1 25 10.00 U idivw %si +# CHECK-NEXT: 2 30 10.00 * U idivw (%rax) +# CHECK-NEXT: 1 25 10.00 U idivl %edx +# CHECK-NEXT: 2 30 10.00 * U idivl (%rax) +# CHECK-NEXT: 1 25 10.00 U idivq %rcx +# CHECK-NEXT: 2 30 10.00 * U idivq (%rax) +# CHECK-NEXT: 1 3 1.00 imulb %dil +# CHECK-NEXT: 2 8 1.00 * imulb (%rax) +# CHECK-NEXT: 4 4 1.33 imulw %di +# CHECK-NEXT: 5 9 1.33 * imulw (%rax) +# CHECK-NEXT: 1 3 1.00 imulw %si, %di +# CHECK-NEXT: 2 8 1.00 * imulw (%rax), %di +# CHECK-NEXT: 2 4 1.00 imulw $511, %si, %di +# CHECK-NEXT: 3 8 1.00 * imulw $511, (%rax), %di +# CHECK-NEXT: 2 4 1.00 imulw $7, %si, %di +# CHECK-NEXT: 3 8 1.00 * imulw $7, (%rax), %di +# CHECK-NEXT: 3 4 1.00 imull %edi +# CHECK-NEXT: 4 9 1.00 * imull (%rax) +# CHECK-NEXT: 1 3 1.00 imull %esi, %edi +# CHECK-NEXT: 2 8 1.00 * imull (%rax), %edi +# CHECK-NEXT: 1 3 1.00 imull $665536, %esi, %edi +# CHECK-NEXT: 2 8 1.00 * imull $665536, (%rax), %edi +# CHECK-NEXT: 1 3 1.00 imull $7, %esi, %edi +# CHECK-NEXT: 2 8 1.00 * imull $7, (%rax), %edi +# CHECK-NEXT: 2 4 1.00 imulq %rdi +# CHECK-NEXT: 3 9 1.00 * imulq (%rax) +# CHECK-NEXT: 1 3 1.00 imulq %rsi, %rdi +# CHECK-NEXT: 2 8 1.00 * imulq (%rax), %rdi +# CHECK-NEXT: 1 3 1.00 imulq $665536, %rsi, %rdi +# CHECK-NEXT: 2 8 1.00 * imulq $665536, (%rax), %rdi +# CHECK-NEXT: 1 3 1.00 imulq $7, %rsi, %rdi +# CHECK-NEXT: 2 8 1.00 * imulq $7, (%rax), %rdi +# CHECK-NEXT: 1 100 0.33 U inb $7, %al +# CHECK-NEXT: 1 100 0.33 U inb %dx, %al +# CHECK-NEXT: 1 100 0.33 U inw $7, %ax +# CHECK-NEXT: 1 100 0.33 U inw %dx, %ax +# CHECK-NEXT: 1 100 0.33 U inl $7, %eax +# CHECK-NEXT: 1 100 0.33 U inl %dx, %eax +# CHECK-NEXT: 1 1 0.33 incb %dil +# CHECK-NEXT: 3 7 1.00 * * incb (%rax) +# CHECK-NEXT: 1 1 0.33 incw %di +# CHECK-NEXT: 3 7 1.00 * * incw (%rax) +# CHECK-NEXT: 1 1 0.33 incl %edi +# CHECK-NEXT: 3 7 1.00 * * incl (%rax) +# CHECK-NEXT: 1 1 0.33 incq %rdi +# CHECK-NEXT: 3 7 1.00 * * incq (%rax) +# CHECK-NEXT: 1 100 0.33 U insb %dx, %es:(%rdi) +# CHECK-NEXT: 1 100 0.33 U insw %dx, %es:(%rdi) +# CHECK-NEXT: 1 100 0.33 U insl %dx, %es:(%rdi) +# CHECK-NEXT: 1 100 0.33 * * U int $7 +# CHECK-NEXT: 1 100 0.33 U invlpg (%rax) +# CHECK-NEXT: 1 100 0.33 U invlpga %rax, %ecx +# CHECK-NEXT: 1 1 0.50 lahf +# CHECK-NEXT: 3 7 0.67 * leave +# CHECK-NEXT: 3 7 0.67 U lodsb (%rsi), %al +# CHECK-NEXT: 3 7 0.67 U lodsw (%rsi), %ax +# CHECK-NEXT: 2 6 0.50 U lodsl (%rsi), %eax +# CHECK-NEXT: 2 6 0.50 U lodsq (%rsi), %rax +# CHECK-NEXT: 5 8 1.00 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 8 1.00 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 8 1.00 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 8 1.00 U movsq (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 1 0.33 movsbw %al, %di +# CHECK-NEXT: 1 1 0.33 movzbw %al, %di +# CHECK-NEXT: 1 5 0.50 * movsbw (%rax), %di +# CHECK-NEXT: 1 5 0.50 * movzbw (%rax), %di +# CHECK-NEXT: 1 1 0.33 movsbl %al, %edi +# CHECK-NEXT: 1 1 0.33 movzbl %al, %edi +# CHECK-NEXT: 1 5 0.50 * movsbl (%rax), %edi +# CHECK-NEXT: 1 5 0.50 * movzbl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 movsbq %al, %rdi +# CHECK-NEXT: 1 1 0.33 movzbq %al, %rdi +# CHECK-NEXT: 1 5 0.50 * movsbq (%rax), %rdi +# CHECK-NEXT: 1 5 0.50 * movzbq (%rax), %rdi +# CHECK-NEXT: 1 1 0.33 movswl %ax, %edi +# CHECK-NEXT: 1 1 0.33 movzwl %ax, %edi +# CHECK-NEXT: 1 5 0.50 * movswl (%rax), %edi +# CHECK-NEXT: 1 5 0.50 * movzwl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 movswq %ax, %rdi +# CHECK-NEXT: 1 1 0.33 movzwq %ax, %rdi +# CHECK-NEXT: 1 5 0.50 * movswq (%rax), %rdi +# CHECK-NEXT: 1 5 0.50 * movzwq (%rax), %rdi +# CHECK-NEXT: 1 1 0.33 movslq %eax, %rdi +# CHECK-NEXT: 1 5 0.50 * movslq (%rax), %rdi +# CHECK-NEXT: 1 3 1.00 mulb %dil +# CHECK-NEXT: 2 8 1.00 * mulb (%rax) +# CHECK-NEXT: 4 4 1.33 mulw %si +# CHECK-NEXT: 5 9 1.33 * mulw (%rax) +# CHECK-NEXT: 3 4 1.00 mull %edx +# CHECK-NEXT: 4 9 1.00 * mull (%rax) +# CHECK-NEXT: 2 4 1.00 mulq %rcx +# CHECK-NEXT: 3 9 1.00 * mulq (%rax) +# CHECK-NEXT: 1 1 0.33 negb %dil +# CHECK-NEXT: 3 7 1.00 * * negb (%r8) +# CHECK-NEXT: 1 1 0.33 negw %si +# CHECK-NEXT: 3 7 1.00 * * negw (%r9) +# CHECK-NEXT: 1 1 0.33 negl %edx +# CHECK-NEXT: 3 7 1.00 * * negl (%rax) +# CHECK-NEXT: 1 1 0.33 negq %rcx +# CHECK-NEXT: 3 7 1.00 * * negq (%r10) +# CHECK-NEXT: 1 1 0.25 nop +# CHECK-NEXT: 1 1 0.25 nopw %di +# CHECK-NEXT: 1 1 0.25 nopw (%rcx) +# CHECK-NEXT: 1 1 0.25 nopl %esi +# CHECK-NEXT: 1 1 0.25 nopl (%r8) +# CHECK-NEXT: 1 1 0.25 nopq %rdx +# CHECK-NEXT: 1 1 0.25 nopq (%r9) +# CHECK-NEXT: 1 1 0.33 notb %dil +# CHECK-NEXT: 3 7 1.00 * * notb (%r8) +# CHECK-NEXT: 1 1 0.33 notw %si +# CHECK-NEXT: 3 7 1.00 * * notw (%r9) +# CHECK-NEXT: 1 1 0.33 notl %edx +# CHECK-NEXT: 3 7 1.00 * * notl (%rax) +# CHECK-NEXT: 1 1 0.33 notq %rcx +# CHECK-NEXT: 3 7 1.00 * * notq (%r10) +# CHECK-NEXT: 1 1 0.33 orb $7, %al +# CHECK-NEXT: 1 1 0.33 orb $7, %dil +# CHECK-NEXT: 3 7 1.00 * * orb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 orb %sil, %dil +# CHECK-NEXT: 3 7 1.00 * * orb %sil, (%rax) +# CHECK-NEXT: 2 6 0.50 * orb (%rax), %dil +# CHECK-NEXT: 1 1 0.33 orw $511, %ax +# CHECK-NEXT: 1 1 0.33 orw $511, %di +# CHECK-NEXT: 3 7 1.00 * * orw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 orw $7, %di +# CHECK-NEXT: 3 7 1.00 * * orw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 orw %si, %di +# CHECK-NEXT: 3 7 1.00 * * orw %si, (%rax) +# CHECK-NEXT: 2 6 0.50 * orw (%rax), %di +# CHECK-NEXT: 1 1 0.33 orl $665536, %eax +# CHECK-NEXT: 1 1 0.33 orl $665536, %edi +# CHECK-NEXT: 3 7 1.00 * * orl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 orl $7, %edi +# CHECK-NEXT: 3 7 1.00 * * orl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 orl %esi, %edi +# CHECK-NEXT: 3 7 1.00 * * orl %esi, (%rax) +# CHECK-NEXT: 2 6 0.50 * orl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 orq $665536, %rax +# CHECK-NEXT: 1 1 0.33 orq $665536, %rdi +# CHECK-NEXT: 3 7 1.00 * * orq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 orq $7, %rdi +# CHECK-NEXT: 3 7 1.00 * * orq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 orq %rsi, %rdi +# CHECK-NEXT: 3 7 1.00 * * orq %rsi, (%rax) +# CHECK-NEXT: 2 6 0.50 * orq (%rax), %rdi +# CHECK-NEXT: 1 100 0.33 U outb %al, $7 +# CHECK-NEXT: 1 100 0.33 U outb %al, %dx +# CHECK-NEXT: 1 100 0.33 U outw %ax, $7 +# CHECK-NEXT: 1 100 0.33 U outw %ax, %dx +# CHECK-NEXT: 1 100 0.33 U outl %eax, $7 +# CHECK-NEXT: 1 100 0.33 U outl %eax, %dx +# CHECK-NEXT: 1 100 0.33 U outsb (%rsi), %dx +# CHECK-NEXT: 1 100 0.33 U outsw (%rsi), %dx +# CHECK-NEXT: 1 100 0.33 U outsl (%rsi), %dx +# CHECK-NEXT: 4 4 1.33 * * U pause +# CHECK-NEXT: 3 2 1.50 rclb %dil +# CHECK-NEXT: 3 2 1.50 rcrb %dil +# CHECK-NEXT: 11 11 3.50 * rclb (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrb (%rax) +# CHECK-NEXT: 8 5 4.00 rclb $7, %dil +# CHECK-NEXT: 8 5 4.00 rcrb $7, %dil +# CHECK-NEXT: 11 11 3.50 * rclb $7, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrb $7, (%rax) +# CHECK-NEXT: 8 5 4.00 rclb %cl, %dil +# CHECK-NEXT: 8 5 4.00 rcrb %cl, %dil +# CHECK-NEXT: 11 11 3.50 * rclb %cl, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrb %cl, (%rax) +# CHECK-NEXT: 3 2 1.50 rclw %di +# CHECK-NEXT: 3 2 1.50 rcrw %di +# CHECK-NEXT: 11 11 3.50 * rclw (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrw (%rax) +# CHECK-NEXT: 8 5 4.00 rclw $7, %di +# CHECK-NEXT: 8 5 4.00 rcrw $7, %di +# CHECK-NEXT: 11 11 3.50 * rclw $7, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrw $7, (%rax) +# CHECK-NEXT: 8 5 4.00 rclw %cl, %di +# CHECK-NEXT: 8 5 4.00 rcrw %cl, %di +# CHECK-NEXT: 11 11 3.50 * rclw %cl, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrw %cl, (%rax) +# CHECK-NEXT: 3 2 1.50 rcll %edi +# CHECK-NEXT: 3 2 1.50 rcrl %edi +# CHECK-NEXT: 11 11 3.50 * rcll (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrl (%rax) +# CHECK-NEXT: 8 5 4.00 rcll $7, %edi +# CHECK-NEXT: 8 5 4.00 rcrl $7, %edi +# CHECK-NEXT: 11 11 3.50 * rcll $7, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrl $7, (%rax) +# CHECK-NEXT: 8 5 4.00 rcll %cl, %edi +# CHECK-NEXT: 8 5 4.00 rcrl %cl, %edi +# CHECK-NEXT: 11 11 3.50 * rcll %cl, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrl %cl, (%rax) +# CHECK-NEXT: 3 2 1.50 rclq %rdi +# CHECK-NEXT: 3 2 1.50 rcrq %rdi +# CHECK-NEXT: 11 11 3.50 * rclq (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrq (%rax) +# CHECK-NEXT: 8 5 4.00 rclq $7, %rdi +# CHECK-NEXT: 8 5 4.00 rcrq $7, %rdi +# CHECK-NEXT: 11 11 3.50 * rclq $7, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrq $7, (%rax) +# CHECK-NEXT: 8 5 4.00 rclq %cl, %rdi +# CHECK-NEXT: 8 5 4.00 rcrq %cl, %rdi +# CHECK-NEXT: 11 11 3.50 * rclq %cl, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrq %cl, (%rax) +# CHECK-NEXT: 1 100 0.33 U rdmsr +# CHECK-NEXT: 1 100 0.33 U rdpmc +# CHECK-NEXT: 1 100 0.33 U rdtsc +# CHECK-NEXT: 1 100 0.33 U rdtscp +# CHECK-NEXT: 2 2 1.00 rolb %dil +# CHECK-NEXT: 2 2 1.00 rorb %dil +# CHECK-NEXT: 5 8 1.00 * * rolb (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorb (%rax) +# CHECK-NEXT: 2 2 1.00 rolb $7, %dil +# CHECK-NEXT: 2 2 1.00 rorb $7, %dil +# CHECK-NEXT: 5 8 1.00 * * rolb $7, (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorb $7, (%rax) +# CHECK-NEXT: 3 3 1.50 rolb %cl, %dil +# CHECK-NEXT: 3 3 1.50 rorb %cl, %dil +# CHECK-NEXT: 6 9 1.50 * * rolb %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * rorb %cl, (%rax) +# CHECK-NEXT: 2 2 1.00 rolw %di +# CHECK-NEXT: 2 2 1.00 rorw %di +# CHECK-NEXT: 5 8 1.00 * * rolw (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorw (%rax) +# CHECK-NEXT: 2 2 1.00 rolw $7, %di +# CHECK-NEXT: 2 2 1.00 rorw $7, %di +# CHECK-NEXT: 5 8 1.00 * * rolw $7, (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorw $7, (%rax) +# CHECK-NEXT: 3 3 1.50 rolw %cl, %di +# CHECK-NEXT: 3 3 1.50 rorw %cl, %di +# CHECK-NEXT: 6 9 1.50 * * rolw %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * rorw %cl, (%rax) +# CHECK-NEXT: 2 2 1.00 roll %edi +# CHECK-NEXT: 2 2 1.00 rorl %edi +# CHECK-NEXT: 5 8 1.00 * * roll (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorl (%rax) +# CHECK-NEXT: 2 2 1.00 roll $7, %edi +# CHECK-NEXT: 2 2 1.00 rorl $7, %edi +# CHECK-NEXT: 5 8 1.00 * * roll $7, (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorl $7, (%rax) +# CHECK-NEXT: 3 3 1.50 roll %cl, %edi +# CHECK-NEXT: 3 3 1.50 rorl %cl, %edi +# CHECK-NEXT: 6 9 1.50 * * roll %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * rorl %cl, (%rax) +# CHECK-NEXT: 2 2 1.00 rolq %rdi +# CHECK-NEXT: 2 2 1.00 rorq %rdi +# CHECK-NEXT: 5 8 1.00 * * rolq (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorq (%rax) +# CHECK-NEXT: 2 2 1.00 rolq $7, %rdi +# CHECK-NEXT: 2 2 1.00 rorq $7, %rdi +# CHECK-NEXT: 5 8 1.00 * * rolq $7, (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorq $7, (%rax) +# CHECK-NEXT: 3 3 1.50 rolq %cl, %rdi +# CHECK-NEXT: 3 3 1.50 rorq %cl, %rdi +# CHECK-NEXT: 6 9 1.50 * * rolq %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * rorq %cl, (%rax) +# CHECK-NEXT: 1 1 0.50 sahf +# CHECK-NEXT: 1 1 0.50 sarb %dil +# CHECK-NEXT: 1 1 0.50 shlb %dil +# CHECK-NEXT: 1 1 0.50 shrb %dil +# CHECK-NEXT: 4 7 1.00 * * sarb (%rax) +# CHECK-NEXT: 4 7 1.00 * * shlb (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrb (%rax) +# CHECK-NEXT: 1 1 0.50 sarb $7, %dil +# CHECK-NEXT: 1 1 0.50 shlb $7, %dil +# CHECK-NEXT: 1 1 0.50 shrb $7, %dil +# CHECK-NEXT: 4 7 1.00 * * sarb $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shlb $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrb $7, (%rax) +# CHECK-NEXT: 3 3 1.50 sarb %cl, %dil +# CHECK-NEXT: 3 3 1.50 shlb %cl, %dil +# CHECK-NEXT: 3 3 1.50 shrb %cl, %dil +# CHECK-NEXT: 6 9 1.50 * * sarb %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shlb %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shrb %cl, (%rax) +# CHECK-NEXT: 1 1 0.50 sarw %di +# CHECK-NEXT: 1 1 0.50 shlw %di +# CHECK-NEXT: 1 1 0.50 shrw %di +# CHECK-NEXT: 4 7 1.00 * * sarw (%rax) +# CHECK-NEXT: 4 7 1.00 * * shlw (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrw (%rax) +# CHECK-NEXT: 1 1 0.50 sarw $7, %di +# CHECK-NEXT: 1 1 0.50 shlw $7, %di +# CHECK-NEXT: 1 1 0.50 shrw $7, %di +# CHECK-NEXT: 4 7 1.00 * * sarw $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shlw $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrw $7, (%rax) +# CHECK-NEXT: 3 3 1.50 sarw %cl, %di +# CHECK-NEXT: 3 3 1.50 shlw %cl, %di +# CHECK-NEXT: 3 3 1.50 shrw %cl, %di +# CHECK-NEXT: 6 9 1.50 * * sarw %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shlw %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shrw %cl, (%rax) +# CHECK-NEXT: 1 1 0.50 sarl %edi +# CHECK-NEXT: 1 1 0.50 shll %edi +# CHECK-NEXT: 1 1 0.50 shrl %edi +# CHECK-NEXT: 4 7 1.00 * * sarl (%rax) +# CHECK-NEXT: 4 7 1.00 * * shll (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrl (%rax) +# CHECK-NEXT: 1 1 0.50 sarl $7, %edi +# CHECK-NEXT: 1 1 0.50 shll $7, %edi +# CHECK-NEXT: 1 1 0.50 shrl $7, %edi +# CHECK-NEXT: 4 7 1.00 * * sarl $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shll $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrl $7, (%rax) +# CHECK-NEXT: 3 3 1.50 sarl %cl, %edi +# CHECK-NEXT: 3 3 1.50 shll %cl, %edi +# CHECK-NEXT: 3 3 1.50 shrl %cl, %edi +# CHECK-NEXT: 6 9 1.50 * * sarl %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shll %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shrl %cl, (%rax) +# CHECK-NEXT: 1 1 0.50 sarq %rdi +# CHECK-NEXT: 1 1 0.50 shlq %rdi +# CHECK-NEXT: 1 1 0.50 shrq %rdi +# CHECK-NEXT: 4 7 1.00 * * sarq (%rax) +# CHECK-NEXT: 4 7 1.00 * * shlq (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrq (%rax) +# CHECK-NEXT: 1 1 0.50 sarq $7, %rdi +# CHECK-NEXT: 1 1 0.50 shlq $7, %rdi +# CHECK-NEXT: 1 1 0.50 shrq $7, %rdi +# CHECK-NEXT: 4 7 1.00 * * sarq $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shlq $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrq $7, (%rax) +# CHECK-NEXT: 3 3 1.50 sarq %cl, %rdi +# CHECK-NEXT: 3 3 1.50 shlq %cl, %rdi +# CHECK-NEXT: 3 3 1.50 shrq %cl, %rdi +# CHECK-NEXT: 6 9 1.50 * * sarq %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shlq %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shrq %cl, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbb $0, %al +# CHECK-NEXT: 2 2 0.67 sbbb $0, %dil +# CHECK-NEXT: 6 9 1.00 * * sbbb $0, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbb $7, %al +# CHECK-NEXT: 2 2 0.67 sbbb $7, %dil +# CHECK-NEXT: 6 9 1.00 * * sbbb $7, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbb %sil, %dil +# CHECK-NEXT: 6 9 1.00 * * sbbb %sil, (%rax) +# CHECK-NEXT: 3 7 0.67 * sbbb (%rax), %dil +# CHECK-NEXT: 2 2 0.67 sbbw $0, %ax +# CHECK-NEXT: 2 2 0.67 sbbw $0, %di +# CHECK-NEXT: 6 9 1.00 * * sbbw $0, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbw $511, %ax +# CHECK-NEXT: 2 2 0.67 sbbw $511, %di +# CHECK-NEXT: 6 9 1.00 * * sbbw $511, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbw $7, %di +# CHECK-NEXT: 6 9 1.00 * * sbbw $7, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbw %si, %di +# CHECK-NEXT: 6 9 1.00 * * sbbw %si, (%rax) +# CHECK-NEXT: 3 7 0.67 * sbbw (%rax), %di +# CHECK-NEXT: 2 2 0.67 sbbl $0, %eax +# CHECK-NEXT: 2 2 0.67 sbbl $0, %edi +# CHECK-NEXT: 6 9 1.00 * * sbbl $0, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbl $665536, %eax +# CHECK-NEXT: 2 2 0.67 sbbl $665536, %edi +# CHECK-NEXT: 6 9 1.00 * * sbbl $665536, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbl $7, %edi +# CHECK-NEXT: 6 9 1.00 * * sbbl $7, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbl %esi, %edi +# CHECK-NEXT: 6 9 1.00 * * sbbl %esi, (%rax) +# CHECK-NEXT: 3 7 0.67 * sbbl (%rax), %edi +# CHECK-NEXT: 2 2 0.67 sbbq $0, %rax +# CHECK-NEXT: 2 2 0.67 sbbq $0, %rdi +# CHECK-NEXT: 6 9 1.00 * * sbbq $0, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbq $665536, %rax +# CHECK-NEXT: 2 2 0.67 sbbq $665536, %rdi +# CHECK-NEXT: 6 9 1.00 * * sbbq $665536, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbq $7, %rdi +# CHECK-NEXT: 6 9 1.00 * * sbbq $7, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbq %rsi, %rdi +# CHECK-NEXT: 6 9 1.00 * * sbbq %rsi, (%rax) +# CHECK-NEXT: 3 7 0.67 * sbbq (%rax), %rdi +# CHECK-NEXT: 2 2 0.67 U scasb %es:(%rdi), %al +# CHECK-NEXT: 2 2 0.67 U scasw %es:(%rdi), %ax +# CHECK-NEXT: 2 2 0.67 U scasl %es:(%rdi), %eax +# CHECK-NEXT: 2 2 0.67 U scasq %es:(%rdi), %rax +# CHECK-NEXT: 1 1 0.50 seto %al +# CHECK-NEXT: 3 2 1.00 * seto (%rax) +# CHECK-NEXT: 1 1 0.50 setno %al +# CHECK-NEXT: 3 2 1.00 * setno (%rax) +# CHECK-NEXT: 1 1 0.50 setb %al +# CHECK-NEXT: 3 2 1.00 * setb (%rax) +# CHECK-NEXT: 1 1 0.50 setae %al +# CHECK-NEXT: 3 2 1.00 * setae (%rax) +# CHECK-NEXT: 1 1 0.50 sete %al +# CHECK-NEXT: 3 2 1.00 * sete (%rax) +# CHECK-NEXT: 1 1 0.50 setne %al +# CHECK-NEXT: 3 2 1.00 * setne (%rax) +# CHECK-NEXT: 2 2 1.00 seta %al +# CHECK-NEXT: 4 3 1.00 * seta (%rax) +# CHECK-NEXT: 2 2 1.00 setbe %al +# CHECK-NEXT: 4 3 1.00 * setbe (%rax) +# CHECK-NEXT: 1 1 0.50 sets %al +# CHECK-NEXT: 3 2 1.00 * sets (%rax) +# CHECK-NEXT: 1 1 0.50 setns %al +# CHECK-NEXT: 3 2 1.00 * setns (%rax) +# CHECK-NEXT: 1 1 0.50 setp %al +# CHECK-NEXT: 3 2 1.00 * setp (%rax) +# CHECK-NEXT: 1 1 0.50 setnp %al +# CHECK-NEXT: 3 2 1.00 * setnp (%rax) +# CHECK-NEXT: 1 1 0.50 setl %al +# CHECK-NEXT: 3 2 1.00 * setl (%rax) +# CHECK-NEXT: 1 1 0.50 setge %al +# CHECK-NEXT: 3 2 1.00 * setge (%rax) +# CHECK-NEXT: 1 1 0.50 setg %al +# CHECK-NEXT: 3 2 1.00 * setg (%rax) +# CHECK-NEXT: 1 1 0.50 setle %al +# CHECK-NEXT: 3 2 1.00 * setle (%rax) +# CHECK-NEXT: 4 4 1.50 shldw %cl, %si, %di +# CHECK-NEXT: 4 4 1.50 shrdw %cl, %si, %di +# CHECK-NEXT: 7 10 1.50 * * shldw %cl, %si, (%rax) +# CHECK-NEXT: 7 10 1.50 * * shrdw %cl, %si, (%rax) +# CHECK-NEXT: 2 2 0.67 shldw $7, %si, %di +# CHECK-NEXT: 2 2 0.67 shrdw $7, %si, %di +# CHECK-NEXT: 5 8 1.00 * * shldw $7, %si, (%rax) +# CHECK-NEXT: 5 8 1.00 * * shrdw $7, %si, (%rax) +# CHECK-NEXT: 4 4 1.50 shldl %cl, %esi, %edi +# CHECK-NEXT: 4 4 1.50 shrdl %cl, %esi, %edi +# CHECK-NEXT: 7 10 1.50 * * shldl %cl, %esi, (%rax) +# CHECK-NEXT: 7 10 1.50 * * shrdl %cl, %esi, (%rax) +# CHECK-NEXT: 2 2 0.67 shldl $7, %esi, %edi +# CHECK-NEXT: 2 2 0.67 shrdl $7, %esi, %edi +# CHECK-NEXT: 5 8 1.00 * * shldl $7, %esi, (%rax) +# CHECK-NEXT: 5 8 1.00 * * shrdl $7, %esi, (%rax) +# CHECK-NEXT: 4 4 1.50 shldq %cl, %rsi, %rdi +# CHECK-NEXT: 4 4 1.50 shrdq %cl, %rsi, %rdi +# CHECK-NEXT: 7 10 1.50 * * shldq %cl, %rsi, (%rax) +# CHECK-NEXT: 7 10 1.50 * * shrdq %cl, %rsi, (%rax) +# CHECK-NEXT: 2 2 0.67 shldq $7, %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 shrdq $7, %rsi, %rdi +# CHECK-NEXT: 5 8 1.00 * * shldq $7, %rsi, (%rax) +# CHECK-NEXT: 5 8 1.00 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 1 0.33 U stc +# CHECK-NEXT: 1 1 0.33 U std +# CHECK-NEXT: 3 5 1.00 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 3 5 1.00 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 3 5 1.00 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 3 5 1.00 U stosq %rax, %es:(%rdi) +# CHECK-NEXT: 1 1 0.33 subb $7, %al +# CHECK-NEXT: 1 1 0.33 subb $7, %dil +# CHECK-NEXT: 3 7 1.00 * * subb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 subb %sil, %dil +# CHECK-NEXT: 3 7 1.00 * * subb %sil, (%rax) +# CHECK-NEXT: 2 6 0.50 * subb (%rax), %dil +# CHECK-NEXT: 1 1 0.33 subw $511, %ax +# CHECK-NEXT: 1 1 0.33 subw $511, %di +# CHECK-NEXT: 3 7 1.00 * * subw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 subw $7, %di +# CHECK-NEXT: 3 7 1.00 * * subw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 subw %si, %di +# CHECK-NEXT: 3 7 1.00 * * subw %si, (%rax) +# CHECK-NEXT: 2 6 0.50 * subw (%rax), %di +# CHECK-NEXT: 1 1 0.33 subl $665536, %eax +# CHECK-NEXT: 1 1 0.33 subl $665536, %edi +# CHECK-NEXT: 3 7 1.00 * * subl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 subl $7, %edi +# CHECK-NEXT: 3 7 1.00 * * subl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 subl %esi, %edi +# CHECK-NEXT: 3 7 1.00 * * subl %esi, (%rax) +# CHECK-NEXT: 2 6 0.50 * subl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 subq $665536, %rax +# CHECK-NEXT: 1 1 0.33 subq $665536, %rdi +# CHECK-NEXT: 3 7 1.00 * * subq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 subq $7, %rdi +# CHECK-NEXT: 3 7 1.00 * * subq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 subq %rsi, %rdi +# CHECK-NEXT: 3 7 1.00 * * subq %rsi, (%rax) +# CHECK-NEXT: 2 6 0.50 * subq (%rax), %rdi +# CHECK-NEXT: 1 1 0.33 testb $7, %al +# CHECK-NEXT: 1 1 0.33 testb $7, %dil +# CHECK-NEXT: 2 6 0.50 * testb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 testb %sil, %dil +# CHECK-NEXT: 2 6 0.50 * testb %sil, (%rax) +# CHECK-NEXT: 1 1 0.33 testw $511, %ax +# CHECK-NEXT: 1 1 0.33 testw $511, %di +# CHECK-NEXT: 2 6 0.50 * testw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 testw $7, %di +# CHECK-NEXT: 2 6 0.50 * testw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 testw %si, %di +# CHECK-NEXT: 2 6 0.50 * testw %si, (%rax) +# CHECK-NEXT: 1 1 0.33 testl $665536, %eax +# CHECK-NEXT: 1 1 0.33 testl $665536, %edi +# CHECK-NEXT: 2 6 0.50 * testl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 testl $7, %edi +# CHECK-NEXT: 2 6 0.50 * testl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 testl %esi, %edi +# CHECK-NEXT: 2 6 0.50 * testl %esi, (%rax) +# CHECK-NEXT: 1 1 0.33 testq $665536, %rax +# CHECK-NEXT: 1 1 0.33 testq $665536, %rdi +# CHECK-NEXT: 2 6 0.50 * testq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 testq $7, %rdi +# CHECK-NEXT: 2 6 0.50 * testq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 testq %rsi, %rdi +# CHECK-NEXT: 2 6 0.50 * testq %rsi, (%rax) +# CHECK-NEXT: 1 100 0.33 * U ud2 +# CHECK-NEXT: 1 100 0.33 U wrmsr +# CHECK-NEXT: 3 2 1.00 xaddb %bl, %cl +# CHECK-NEXT: 5 8 1.00 * * xaddb %bl, (%rcx) +# CHECK-NEXT: 3 2 1.00 xaddw %bx, %cx +# CHECK-NEXT: 5 8 1.00 * * xaddw %ax, (%rbx) +# CHECK-NEXT: 3 2 1.00 xaddl %ebx, %ecx +# CHECK-NEXT: 5 8 1.00 * * xaddl %eax, (%rbx) +# CHECK-NEXT: 3 2 1.00 xaddq %rbx, %rcx +# CHECK-NEXT: 5 8 1.00 * * xaddq %rax, (%rbx) +# CHECK-NEXT: 3 2 1.00 xchgb %bl, %cl +# CHECK-NEXT: 3 6 1.00 * * xchgb %bl, (%rbx) +# CHECK-NEXT: 3 2 1.00 xchgw %bx, %ax +# CHECK-NEXT: 3 2 1.00 xchgw %bx, %cx +# CHECK-NEXT: 3 6 1.00 * * xchgw %ax, (%rbx) +# CHECK-NEXT: 3 2 1.00 xchgl %ebx, %eax +# CHECK-NEXT: 3 2 1.00 xchgl %ebx, %ecx +# CHECK-NEXT: 3 6 1.00 * * xchgl %eax, (%rbx) +# CHECK-NEXT: 3 2 1.00 xchgq %rbx, %rax +# CHECK-NEXT: 3 2 1.00 xchgq %rbx, %rcx +# CHECK-NEXT: 3 6 1.00 * * xchgq %rax, (%rbx) +# CHECK-NEXT: 1 5 0.50 * xlatb +# CHECK-NEXT: 1 1 0.33 xorb $7, %al +# CHECK-NEXT: 1 1 0.33 xorb $7, %dil +# CHECK-NEXT: 3 7 1.00 * * xorb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 xorb %sil, %dil +# CHECK-NEXT: 3 7 1.00 * * xorb %sil, (%rax) +# CHECK-NEXT: 2 6 0.50 * xorb (%rax), %dil +# CHECK-NEXT: 1 1 0.33 xorw $511, %ax +# CHECK-NEXT: 1 1 0.33 xorw $511, %di +# CHECK-NEXT: 3 7 1.00 * * xorw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 xorw $7, %di +# CHECK-NEXT: 3 7 1.00 * * xorw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 xorw %si, %di +# CHECK-NEXT: 3 7 1.00 * * xorw %si, (%rax) +# CHECK-NEXT: 2 6 0.50 * xorw (%rax), %di +# CHECK-NEXT: 1 1 0.33 xorl $665536, %eax +# CHECK-NEXT: 1 1 0.33 xorl $665536, %edi +# CHECK-NEXT: 3 7 1.00 * * xorl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 xorl $7, %edi +# CHECK-NEXT: 3 7 1.00 * * xorl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 xorl %esi, %edi +# CHECK-NEXT: 3 7 1.00 * * xorl %esi, (%rax) +# CHECK-NEXT: 2 6 0.50 * xorl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 xorq $665536, %rax +# CHECK-NEXT: 1 1 0.33 xorq $665536, %rdi +# CHECK-NEXT: 3 7 1.00 * * xorq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 xorq $7, %rdi +# CHECK-NEXT: 3 7 1.00 * * xorq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 xorq %rsi, %rdi +# CHECK-NEXT: 3 7 1.00 * * xorq %rsi, (%rax) +# CHECK-NEXT: 2 6 0.50 * xorq (%rax), %rdi + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: 160.00 - 596.50 238.00 230.00 596.50 324.50 324.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb $0, %al +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb $0, %dil +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcb $0, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb $7, %al +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb $7, %dil +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcb $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb %sil, %dil +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 adcb %sil, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcb (%rax), %dil +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $0, %ax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $0, %di +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcw $0, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $511, %ax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $511, %di +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcw $511, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $7, %di +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcw $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw %si, %di +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 adcw %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $0, %eax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $0, %edi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcl $0, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $665536, %eax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $665536, %edi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcl $665536, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $7, %edi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcl $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl %esi, %edi +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 adcl %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $0, %rax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $0, %rdi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcq $0, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $665536, %rax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $665536, %rdi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcq $665536, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $7, %rdi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcq $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq %rsi, %rdi +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 adcq %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcq (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 addb (%rax), %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addw $511, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addw $7, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addw %si, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 addw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 addl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 addq (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andb (%rax), %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andw $511, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andw $7, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andw %si, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andq (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - - - bsfw %si, %di +# CHECK-NEXT: - - - 1.00 - - - - bsrw %si, %di +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsfw (%rax), %di +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsrw (%rax), %di +# CHECK-NEXT: - - - 1.00 - - - - bsfl %esi, %edi +# CHECK-NEXT: - - - 1.00 - - - - bsrl %esi, %edi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsfl (%rax), %edi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsrl (%rax), %edi +# CHECK-NEXT: - - - 1.00 - - - - bsfq %rsi, %rdi +# CHECK-NEXT: - - - 1.00 - - - - bsrq %rsi, %rdi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsfq (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsrq (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - - - bswapl %eax +# CHECK-NEXT: - - 0.50 1.00 - 0.50 - - bswapq %rax +# CHECK-NEXT: - - 0.50 - - 0.50 - - btw %si, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - btcw %si, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - btrw %si, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - btsw %si, %di +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btw %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btcw %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btrw %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btsw %si, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - btw $7, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - btcw $7, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - btrw $7, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - btsw $7, %di +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 btw $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btcw $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btrw $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btsw $7, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - btl %esi, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btcl %esi, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btrl %esi, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btsl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btl %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btcl %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btrl %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btsl %esi, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - btl $7, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btcl $7, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btrl $7, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btsl $7, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 btl $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btcl $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btrl $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btsl $7, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - btq %rsi, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btcq %rsi, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btrq %rsi, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btsq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btq %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btcq %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btrq %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btsq %rsi, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - btq $7, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btcq $7, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btrq $7, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btsq $7, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 btq $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btcq $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btrq $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btsq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cbtw +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cwtl +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cltq +# CHECK-NEXT: - - 1.33 0.33 - 0.33 - - cwtd +# CHECK-NEXT: - - 0.50 - - 0.50 - - cltd +# CHECK-NEXT: - - 0.50 - - 0.50 - - cqto +# CHECK-NEXT: - - - - - - - - clc +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cld +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmc +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpb (%rax), %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpw $511, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpw $7, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpw %si, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq (%rax), %rdi +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsq %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgb %cl, %bl +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgb %cl, (%rbx) +# CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgw %cx, %bx +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgw %cx, (%rbx) +# CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgl %ecx, %ebx +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgl %ecx, (%rbx) +# CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgq %rcx, %rbx +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgq %rcx, (%rbx) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cpuid +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decb %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decb (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decw %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decw (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decl %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decl (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decq %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decq (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - divb %dil +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 divb (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - divw %si +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 divw (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - divl %edx +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 divl (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - divq %rcx +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 divq (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - enter $7, $4095 +# CHECK-NEXT: 10.00 - 1.00 - - - - - idivb %dil +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 idivb (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - idivw %si +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 idivw (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - idivl %edx +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 idivl (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - idivq %rcx +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 idivq (%rax) +# CHECK-NEXT: - - - 1.00 - - - - imulb %dil +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulb (%rax) +# CHECK-NEXT: - - 1.17 1.67 - 1.17 - - imulw %di +# CHECK-NEXT: - - 1.17 1.67 - 1.17 0.50 0.50 imulw (%rax) +# CHECK-NEXT: - - - 1.00 - - - - imulw %si, %di +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulw (%rax), %di +# CHECK-NEXT: - - 0.33 1.33 - 0.33 - - imulw $511, %si, %di +# CHECK-NEXT: - - 0.33 1.33 - 0.33 0.50 0.50 imulw $511, (%rax), %di +# CHECK-NEXT: - - 0.33 1.33 - 0.33 - - imulw $7, %si, %di +# CHECK-NEXT: - - 0.33 1.33 - 0.33 0.50 0.50 imulw $7, (%rax), %di +# CHECK-NEXT: - - 0.83 1.33 - 0.83 - - imull %edi +# CHECK-NEXT: - - 0.83 1.33 - 0.83 0.50 0.50 imull (%rax) +# CHECK-NEXT: - - - 1.00 - - - - imull %esi, %edi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imull (%rax), %edi +# CHECK-NEXT: - - - 1.00 - - - - imull $665536, %esi, %edi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imull $665536, (%rax), %edi +# CHECK-NEXT: - - - 1.00 - - - - imull $7, %esi, %edi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imull $7, (%rax), %edi +# CHECK-NEXT: - - 1.00 1.00 - - - - imulq %rdi +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 imulq (%rax) +# CHECK-NEXT: - - - 1.00 - - - - imulq %rsi, %rdi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulq (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - - - imulq $665536, %rsi, %rdi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulq $665536, (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - - - imulq $7, %rsi, %rdi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulq $7, (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inb %dx, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inw $7, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inw %dx, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inl $7, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inl %dx, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incb %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incb (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incw %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incw (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incl %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incl (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incq %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incq (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - insb %dx, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - insw %dx, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - insl %dx, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - int $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - invlpg (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - invlpga %rax, %ecx +# CHECK-NEXT: - - 0.50 - - 0.50 - - lahf +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 leave +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 lodsb (%rsi), %al +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 lodsw (%rsi), %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 lodsl (%rsi), %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 lodsq (%rsi), %rax +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsq (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movsbw %al, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzbw %al, %di +# CHECK-NEXT: - - - - - - 0.50 0.50 movsbw (%rax), %di +# CHECK-NEXT: - - - - - - 0.50 0.50 movzbw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movsbl %al, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzbl %al, %edi +# CHECK-NEXT: - - - - - - 0.50 0.50 movsbl (%rax), %edi +# CHECK-NEXT: - - - - - - 0.50 0.50 movzbl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movsbq %al, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzbq %al, %rdi +# CHECK-NEXT: - - - - - - 0.50 0.50 movsbq (%rax), %rdi +# CHECK-NEXT: - - - - - - 0.50 0.50 movzbq (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movswl %ax, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzwl %ax, %edi +# CHECK-NEXT: - - - - - - 0.50 0.50 movswl (%rax), %edi +# CHECK-NEXT: - - - - - - 0.50 0.50 movzwl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movswq %ax, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzwq %ax, %rdi +# CHECK-NEXT: - - - - - - 0.50 0.50 movswq (%rax), %rdi +# CHECK-NEXT: - - - - - - 0.50 0.50 movzwq (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movslq %eax, %rdi +# CHECK-NEXT: - - - - - - 0.50 0.50 movslq (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - - - mulb %dil +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 mulb (%rax) +# CHECK-NEXT: - - 1.17 1.67 - 1.17 - - mulw %si +# CHECK-NEXT: - - 1.17 1.67 - 1.17 0.50 0.50 mulw (%rax) +# CHECK-NEXT: - - 0.83 1.33 - 0.83 - - mull %edx +# CHECK-NEXT: - - 0.83 1.33 - 0.83 0.50 0.50 mull (%rax) +# CHECK-NEXT: - - 1.00 1.00 - - - - mulq %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 mulq (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - negb %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 negb (%r8) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - negw %si +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 negw (%r9) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - negl %edx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 negl (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - negq %rcx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 negq (%r10) +# CHECK-NEXT: - - - - - - - - nop +# CHECK-NEXT: - - - - - - - - nopw %di +# CHECK-NEXT: - - - - - - - - nopw (%rcx) +# CHECK-NEXT: - - - - - - - - nopl %esi +# CHECK-NEXT: - - - - - - - - nopl (%r8) +# CHECK-NEXT: - - - - - - - - nopq %rdx +# CHECK-NEXT: - - - - - - - - nopq (%r9) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - notb %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 notb (%r8) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - notw %si +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 notw (%r9) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - notl %edx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 notl (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - notq %rcx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 notq (%r10) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 orb (%rax), %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orw $511, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orw $7, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orw %si, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 orw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 orl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 orq (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outb %al, $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outb %al, %dx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outw %ax, $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outw %ax, %dx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outl %eax, $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outl %eax, %dx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outsb (%rsi), %dx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outsw (%rsi), %dx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outsl (%rsi), %dx +# CHECK-NEXT: - - 1.00 1.00 - 2.00 - - pause +# CHECK-NEXT: - - 1.50 - - 1.50 - - rclb %dil +# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrb %dil +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclb (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrb (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rclb $7, %dil +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrb $7, %dil +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclb $7, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrb $7, (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rclb %cl, %dil +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrb %cl, %dil +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclb %cl, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrb %cl, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - rclw %di +# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrw %di +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclw (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrw (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rclw $7, %di +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrw $7, %di +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclw $7, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrw $7, (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rclw %cl, %di +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrw %cl, %di +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclw %cl, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrw %cl, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - rcll %edi +# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrl %edi +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcll (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrl (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcll $7, %edi +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrl $7, %edi +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcll $7, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrl $7, (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcll %cl, %edi +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrl %cl, %edi +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcll %cl, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrl %cl, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - rclq %rdi +# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrq %rdi +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclq (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrq (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rclq $7, %rdi +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrq $7, %rdi +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclq $7, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrq $7, (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rclq %cl, %rdi +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrq %cl, %rdi +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclq %cl, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrq %cl, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - rdmsr +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - rdpmc +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - rdtsc +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - rdtscp +# CHECK-NEXT: - - 1.00 - - 1.00 - - rolb %dil +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorb %dil +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolb (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorb (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - rolb $7, %dil +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorb $7, %dil +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolb $7, (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorb $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - rolb %cl, %dil +# CHECK-NEXT: - - 1.50 - - 1.50 - - rorb %cl, %dil +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rolb %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rorb %cl, (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - rolw %di +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorw %di +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolw (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorw (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - rolw $7, %di +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorw $7, %di +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolw $7, (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorw $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - rolw %cl, %di +# CHECK-NEXT: - - 1.50 - - 1.50 - - rorw %cl, %di +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rolw %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rorw %cl, (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - roll %edi +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorl %edi +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 roll (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorl (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - roll $7, %edi +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorl $7, %edi +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 roll $7, (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorl $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - roll %cl, %edi +# CHECK-NEXT: - - 1.50 - - 1.50 - - rorl %cl, %edi +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 roll %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rorl %cl, (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - rolq %rdi +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorq %rdi +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolq (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorq (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - rolq $7, %rdi +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorq $7, %rdi +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolq $7, (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorq $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - rolq %cl, %rdi +# CHECK-NEXT: - - 1.50 - - 1.50 - - rorq %cl, %rdi +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rolq %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rorq %cl, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sahf +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarb %dil +# CHECK-NEXT: - - 0.50 - - 0.50 - - shlb %dil +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrb %dil +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarb (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlb (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrb (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarb $7, %dil +# CHECK-NEXT: - - 0.50 - - 0.50 - - shlb $7, %dil +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrb $7, %dil +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarb $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlb $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrb $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - sarb %cl, %dil +# CHECK-NEXT: - - 1.50 - - 1.50 - - shlb %cl, %dil +# CHECK-NEXT: - - 1.50 - - 1.50 - - shrb %cl, %dil +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 sarb %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shlb %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shrb %cl, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarw %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - shlw %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrw %di +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarw (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlw (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrw (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarw $7, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - shlw $7, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrw $7, %di +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarw $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlw $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrw $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - sarw %cl, %di +# CHECK-NEXT: - - 1.50 - - 1.50 - - shlw %cl, %di +# CHECK-NEXT: - - 1.50 - - 1.50 - - shrw %cl, %di +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 sarw %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shlw %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shrw %cl, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarl %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shll %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrl %edi +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarl (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shll (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrl (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarl $7, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shll $7, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrl $7, %edi +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarl $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shll $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrl $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - sarl %cl, %edi +# CHECK-NEXT: - - 1.50 - - 1.50 - - shll %cl, %edi +# CHECK-NEXT: - - 1.50 - - 1.50 - - shrl %cl, %edi +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 sarl %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shll %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shrl %cl, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarq %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shlq %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrq %rdi +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarq (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlq (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrq (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarq $7, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shlq $7, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrq $7, %rdi +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarq $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlq $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrq $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - sarq %cl, %rdi +# CHECK-NEXT: - - 1.50 - - 1.50 - - shlq %cl, %rdi +# CHECK-NEXT: - - 1.50 - - 1.50 - - shrq %cl, %rdi +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 sarq %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shlq %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shrq %cl, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb $0, %al +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb $0, %dil +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbb $0, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb $7, %al +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb $7, %dil +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbb $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb %sil, %dil +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 sbbb %sil, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 sbbb (%rax), %dil +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $0, %ax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $0, %di +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbw $0, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $511, %ax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $511, %di +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbw $511, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $7, %di +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbw $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw %si, %di +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 sbbw %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 sbbw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $0, %eax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $0, %edi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbl $0, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $665536, %eax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $665536, %edi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbl $665536, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $7, %edi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbl $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl %esi, %edi +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 sbbl %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 sbbl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $0, %rax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $0, %rdi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbq $0, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $665536, %rax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $665536, %rdi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbq $665536, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $7, %rdi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbq $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq %rsi, %rdi +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 sbbq %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 sbbq (%rax), %rdi +# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - scasb %es:(%rdi), %al +# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - scasw %es:(%rdi), %ax +# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - scasl %es:(%rdi), %eax +# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - scasq %es:(%rdi), %rax +# CHECK-NEXT: - - 0.50 - - 0.50 - - seto %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 seto (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setno %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setno (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setb %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setb (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setae %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setae (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sete %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 sete (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setne %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setne (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - seta %al +# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 seta (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - setbe %al +# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 setbe (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sets %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 sets (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setns %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setns (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setp %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setp (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setnp %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setnp (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setl %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setl (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setge %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setge (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setg %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setg (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setle %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setle (%rax) +# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shldw %cl, %si, %di +# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shrdw %cl, %si, %di +# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shldw %cl, %si, (%rax) +# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shrdw %cl, %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shldw $7, %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shrdw $7, %si, %di +# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shldw $7, %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shrdw $7, %si, (%rax) +# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shldl %cl, %esi, %edi +# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shrdl %cl, %esi, %edi +# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shldl %cl, %esi, (%rax) +# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shrdl %cl, %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shldl $7, %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shrdl $7, %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shldl $7, %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shrdl $7, %esi, (%rax) +# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shldq %cl, %rsi, %rdi +# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shrdq %cl, %rsi, %rdi +# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shldq %cl, %rsi, (%rax) +# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shrdq %cl, %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shldq $7, %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shrdq $7, %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shldq $7, %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shrdq $7, %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - stc +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - std +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosb %al, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosw %ax, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosl %eax, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosq %rax, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 subb (%rax), %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subw $511, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subw $7, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subw %si, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 subw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 subl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 subq (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testw $511, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testw $7, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testw %si, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - ud2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - wrmsr +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xaddb %bl, %cl +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 xaddb %bl, (%rcx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xaddw %bx, %cx +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 xaddw %ax, (%rbx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xaddl %ebx, %ecx +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 xaddl %eax, (%rbx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xaddq %rbx, %rcx +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 xaddq %rax, (%rbx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgb %bl, %cl +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xchgb %bl, (%rbx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgw %bx, %ax +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgw %bx, %cx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xchgw %ax, (%rbx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgl %ebx, %eax +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgl %ebx, %ecx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xchgl %eax, (%rbx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgq %rbx, %rax +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgq %rbx, %rcx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xchgq %rax, (%rbx) +# CHECK-NEXT: - - - - - - 0.50 0.50 xlatb +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 xorb (%rax), %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw $511, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw $7, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw %si, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 xorw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 xorl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 xorq (%rax), %rdi diff --git a/test/tools/llvm-mca/X86/Barcelona/resources-x87.s b/test/tools/llvm-mca/X86/Barcelona/resources-x87.s new file mode 100644 index 00000000000..1f3e51e58b3 --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/resources-x87.s @@ -0,0 +1,521 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +f2xm1 + +fabs + +fadd %st, %st(1) +fadd %st(2) +fadds (%ecx) +faddl (%ecx) +faddp %st(1) +faddp %st(2) +fiadds (%ecx) +fiaddl (%ecx) + +fbld (%ecx) +fbstp (%eax) + +fchs + +fnclex + +fcmovb %st(1), %st +fcmovbe %st(1), %st +fcmove %st(1), %st +fcmovnb %st(1), %st +fcmovnbe %st(1), %st +fcmovne %st(1), %st +fcmovnu %st(1), %st +fcmovu %st(1), %st + +fcom %st(1) +fcom %st(3) +fcoms (%ecx) +fcoml (%eax) +fcomp %st(1) +fcomp %st(3) +fcomps (%ecx) +fcompl (%eax) +fcompp + +fcomi %st(3) +fcompi %st(3) + +fcos + +fdecstp + +fdiv %st, %st(1) +fdiv %st(2) +fdivs (%ecx) +fdivl (%eax) +fdivp %st(1) +fdivp %st(2) +fidivs (%ecx) +fidivl (%eax) + +fdivr %st, %st(1) +fdivr %st(2) +fdivrs (%ecx) +fdivrl (%eax) +fdivrp %st(1) +fdivrp %st(2) +fidivrs (%ecx) +fidivrl (%eax) + +ffree %st(0) + +ficoms (%ecx) +ficoml (%eax) +ficomps (%ecx) +ficompl (%eax) + +filds (%edx) +fildl (%ecx) +fildll (%eax) + +fincstp + +fninit + +fists (%edx) +fistl (%ecx) +fistps (%edx) +fistpl (%ecx) +fistpll (%eax) + +fisttps (%edx) +fisttpl (%ecx) +fisttpll (%eax) + +fld %st(0) +flds (%edx) +fldl (%ecx) +fldt (%eax) + +fldcw (%eax) +fldenv (%eax) + +fld1 +fldl2e +fldl2t +fldlg2 +fldln2 +fldpi +fldz + +fmul %st, %st(1) +fmul %st(2) +fmuls (%ecx) +fmull (%eax) +fmulp %st(1) +fmulp %st(2) +fimuls (%ecx) +fimull (%eax) + +fnop + +fpatan + +fprem +fprem1 + +fptan + +frndint + +frstor (%eax) + +fnsave (%eax) + +fscale + +fsin + +fsincos + +fsqrt + +fst %st(0) +fsts (%edx) +fstl (%ecx) +fstp %st(0) +fstpl (%edx) +fstpl (%ecx) +fstpt (%eax) + +fnstcw (%eax) +fnstenv (%eax) +fnstsw (%eax) + +frstor (%eax) +fsave (%eax) + +fsub %st, %st(1) +fsub %st(2) +fsubs (%ecx) +fsubl (%eax) +fsubp %st(1) +fsubp %st(2) +fisubs (%ecx) +fisubl (%eax) + +fsubr %st, %st(1) +fsubr %st(2) +fsubrs (%ecx) +fsubrl (%eax) +fsubrp %st(1) +fsubrp %st(2) +fisubrs (%ecx) +fisubrl (%eax) + +ftst + +fucom %st(1) +fucom %st(3) +fucomp %st(1) +fucomp %st(3) +fucompp + +fucomi %st(3) +fucompi %st(3) + +fwait + +fxam + +fxch %st(1) +fxch %st(3) + +fxrstor (%eax) +fxsave (%eax) + +fxtract + +fyl2x +fyl2xp1 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.33 U f2xm1 +# CHECK-NEXT: 1 1 1.00 U fabs +# CHECK-NEXT: 1 3 1.00 U fadd %st, %st(1) +# CHECK-NEXT: 1 3 1.00 U fadd %st(2), %st +# CHECK-NEXT: 2 10 1.00 * U fadds (%ecx) +# CHECK-NEXT: 2 10 1.00 * U faddl (%ecx) +# CHECK-NEXT: 1 3 1.00 U faddp %st, %st(1) +# CHECK-NEXT: 1 3 1.00 U faddp %st, %st(2) +# CHECK-NEXT: 3 13 2.00 * U fiadds (%ecx) +# CHECK-NEXT: 3 13 2.00 * U fiaddl (%ecx) +# CHECK-NEXT: 1 100 0.33 U fbld (%ecx) +# CHECK-NEXT: 1 100 0.33 U fbstp (%eax) +# CHECK-NEXT: 1 1 1.00 U fchs +# CHECK-NEXT: 1 100 0.33 U fnclex +# CHECK-NEXT: 3 3 2.00 U fcmovb %st(1), %st +# CHECK-NEXT: 3 3 2.00 U fcmovbe %st(1), %st +# CHECK-NEXT: 3 3 2.00 U fcmove %st(1), %st +# CHECK-NEXT: 3 3 2.00 U fcmovnb %st(1), %st +# CHECK-NEXT: 3 3 2.00 U fcmovnbe %st(1), %st +# CHECK-NEXT: 3 3 2.00 U fcmovne %st(1), %st +# CHECK-NEXT: 3 3 2.00 U fcmovnu %st(1), %st +# CHECK-NEXT: 3 3 2.00 U fcmovu %st(1), %st +# CHECK-NEXT: 1 1 1.00 U fcom %st(1) +# CHECK-NEXT: 1 1 1.00 U fcom %st(3) +# CHECK-NEXT: 2 8 1.00 U fcoms (%ecx) +# CHECK-NEXT: 2 8 1.00 U fcoml (%eax) +# CHECK-NEXT: 1 1 1.00 U fcomp %st(1) +# CHECK-NEXT: 1 1 1.00 U fcomp %st(3) +# CHECK-NEXT: 2 8 1.00 U fcomps (%ecx) +# CHECK-NEXT: 2 8 1.00 U fcompl (%eax) +# CHECK-NEXT: 1 100 0.33 U fcompp +# CHECK-NEXT: 3 3 1.00 U fcomi %st(3), %st +# CHECK-NEXT: 3 3 1.00 U fcompi %st(3), %st +# CHECK-NEXT: 1 100 0.33 U fcos +# CHECK-NEXT: 1 1 1.00 U fdecstp +# CHECK-NEXT: 1 14 14.00 U fdiv %st, %st(1) +# CHECK-NEXT: 1 14 14.00 U fdiv %st(2), %st +# CHECK-NEXT: 2 31 1.00 * U fdivs (%ecx) +# CHECK-NEXT: 2 31 1.00 * U fdivl (%eax) +# CHECK-NEXT: 1 14 14.00 U fdivp %st, %st(1) +# CHECK-NEXT: 1 14 14.00 U fdivp %st, %st(2) +# CHECK-NEXT: 3 34 1.00 * U fidivs (%ecx) +# CHECK-NEXT: 3 34 1.00 * U fidivl (%eax) +# CHECK-NEXT: 1 14 14.00 U fdivr %st, %st(1) +# CHECK-NEXT: 1 14 14.00 U fdivr %st(2), %st +# CHECK-NEXT: 2 31 1.00 * U fdivrs (%ecx) +# CHECK-NEXT: 2 31 1.00 * U fdivrl (%eax) +# CHECK-NEXT: 1 14 14.00 U fdivrp %st, %st(1) +# CHECK-NEXT: 1 14 14.00 U fdivrp %st, %st(2) +# CHECK-NEXT: 3 34 1.00 * U fidivrs (%ecx) +# CHECK-NEXT: 3 34 1.00 * U fidivrl (%eax) +# CHECK-NEXT: 1 1 1.00 U ffree %st(0) +# CHECK-NEXT: 3 11 2.00 U ficoms (%ecx) +# CHECK-NEXT: 3 11 2.00 U ficoml (%eax) +# CHECK-NEXT: 3 11 2.00 U ficomps (%ecx) +# CHECK-NEXT: 3 11 2.00 U ficompl (%eax) +# CHECK-NEXT: 2 10 1.00 * U filds (%edx) +# CHECK-NEXT: 2 10 1.00 * U fildl (%ecx) +# CHECK-NEXT: 2 10 1.00 * U fildll (%eax) +# CHECK-NEXT: 1 1 1.00 U fincstp +# CHECK-NEXT: 4 5 1.33 U fninit +# CHECK-NEXT: 4 9 1.00 * U fists (%edx) +# CHECK-NEXT: 4 9 1.00 * U fistl (%ecx) +# CHECK-NEXT: 4 9 1.00 * U fistps (%edx) +# CHECK-NEXT: 4 9 1.00 * U fistpl (%ecx) +# CHECK-NEXT: 4 9 1.00 * U fistpll (%eax) +# CHECK-NEXT: 3 5 1.00 * U fisttps (%edx) +# CHECK-NEXT: 3 5 1.00 * U fisttpl (%ecx) +# CHECK-NEXT: 3 5 1.00 * U fisttpll (%eax) +# CHECK-NEXT: 1 1 1.00 U fld %st(0) +# CHECK-NEXT: 3 9 1.00 * U flds (%edx) +# CHECK-NEXT: 3 9 1.00 * U fldl (%ecx) +# CHECK-NEXT: 3 9 1.00 * U fldt (%eax) +# CHECK-NEXT: 5 8 2.00 * U fldcw (%eax) +# CHECK-NEXT: 1 100 0.33 U fldenv (%eax) +# CHECK-NEXT: 2 1 1.00 U fld1 +# CHECK-NEXT: 2 1 1.00 U fldl2e +# CHECK-NEXT: 2 1 1.00 U fldl2t +# CHECK-NEXT: 2 1 1.00 U fldlg2 +# CHECK-NEXT: 2 1 1.00 U fldln2 +# CHECK-NEXT: 2 1 1.00 U fldpi +# CHECK-NEXT: 1 1 1.00 U fldz +# CHECK-NEXT: 1 5 1.00 U fmul %st, %st(1) +# CHECK-NEXT: 1 5 1.00 U fmul %st(2), %st +# CHECK-NEXT: 2 12 1.00 * U fmuls (%ecx) +# CHECK-NEXT: 2 12 1.00 * U fmull (%eax) +# CHECK-NEXT: 1 5 1.00 U fmulp %st, %st(1) +# CHECK-NEXT: 1 5 1.00 U fmulp %st, %st(2) +# CHECK-NEXT: 3 15 1.00 * U fimuls (%ecx) +# CHECK-NEXT: 3 15 1.00 * U fimull (%eax) +# CHECK-NEXT: 1 1 1.00 U fnop +# CHECK-NEXT: 1 100 0.33 U fpatan +# CHECK-NEXT: 1 100 0.33 U fprem +# CHECK-NEXT: 1 100 0.33 U fprem1 +# CHECK-NEXT: 1 100 0.33 U fptan +# CHECK-NEXT: 1 100 0.33 U frndint +# CHECK-NEXT: 1 100 0.33 U frstor (%eax) +# CHECK-NEXT: 1 100 0.33 U fnsave (%eax) +# CHECK-NEXT: 1 100 0.33 U fscale +# CHECK-NEXT: 1 100 0.33 U fsin +# CHECK-NEXT: 1 100 0.33 U fsincos +# CHECK-NEXT: 1 24 24.00 U fsqrt +# CHECK-NEXT: 1 1 1.00 U fst %st(0) +# CHECK-NEXT: 3 6 1.00 * U fsts (%edx) +# CHECK-NEXT: 3 6 1.00 * U fstl (%ecx) +# CHECK-NEXT: 1 1 1.00 U fstp %st(0) +# CHECK-NEXT: 3 6 1.00 * U fstpl (%edx) +# CHECK-NEXT: 3 6 1.00 * U fstpl (%ecx) +# CHECK-NEXT: 3 6 1.00 * U fstpt (%eax) +# CHECK-NEXT: 4 7 1.00 * U fnstcw (%eax) +# CHECK-NEXT: 1 100 0.33 U fnstenv (%eax) +# CHECK-NEXT: 4 7 1.00 U fnstsw (%eax) +# CHECK-NEXT: 1 100 0.33 U frstor (%eax) +# CHECK-NEXT: 1 100 0.33 U wait +# CHECK-NEXT: 1 100 0.33 U fnsave (%eax) +# CHECK-NEXT: 1 3 1.00 U fsub %st, %st(1) +# CHECK-NEXT: 1 3 1.00 U fsub %st(2), %st +# CHECK-NEXT: 2 10 1.00 * U fsubs (%ecx) +# CHECK-NEXT: 2 10 1.00 * U fsubl (%eax) +# CHECK-NEXT: 1 3 1.00 U fsubp %st, %st(1) +# CHECK-NEXT: 1 3 1.00 U fsubp %st, %st(2) +# CHECK-NEXT: 3 13 2.00 * U fisubs (%ecx) +# CHECK-NEXT: 3 13 2.00 * U fisubl (%eax) +# CHECK-NEXT: 1 3 1.00 U fsubr %st, %st(1) +# CHECK-NEXT: 1 3 1.00 U fsubr %st(2), %st +# CHECK-NEXT: 2 10 1.00 * U fsubrs (%ecx) +# CHECK-NEXT: 2 10 1.00 * U fsubrl (%eax) +# CHECK-NEXT: 1 3 1.00 U fsubrp %st, %st(1) +# CHECK-NEXT: 1 3 1.00 U fsubrp %st, %st(2) +# CHECK-NEXT: 3 13 2.00 * U fisubrs (%ecx) +# CHECK-NEXT: 3 13 2.00 * U fisubrl (%eax) +# CHECK-NEXT: 1 3 1.00 U ftst +# CHECK-NEXT: 1 1 1.00 U fucom %st(1) +# CHECK-NEXT: 1 1 1.00 U fucom %st(3) +# CHECK-NEXT: 1 1 1.00 U fucomp %st(1) +# CHECK-NEXT: 1 1 1.00 U fucomp %st(3) +# CHECK-NEXT: 1 3 1.00 U fucompp +# CHECK-NEXT: 3 3 1.00 U fucomi %st(3), %st +# CHECK-NEXT: 3 3 1.00 U fucompi %st(3), %st +# CHECK-NEXT: 1 100 0.33 U wait +# CHECK-NEXT: 1 100 0.33 U fxam +# CHECK-NEXT: 1 1 0.33 U fxch %st(1) +# CHECK-NEXT: 1 1 0.33 U fxch %st(3) +# CHECK-NEXT: 5 5 2.00 * * U fxrstor (%eax) +# CHECK-NEXT: 1 100 0.33 * * U fxsave (%eax) +# CHECK-NEXT: 1 100 0.33 U fxtract +# CHECK-NEXT: 1 100 0.33 U fyl2x +# CHECK-NEXT: 1 100 0.33 U fyl2xp1 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - 136.00 52.67 90.67 17.00 54.67 34.00 34.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - f2xm1 +# CHECK-NEXT: - - - - - 1.00 - - fabs +# CHECK-NEXT: - - - 1.00 - - - - fadd %st, %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fadd %st(2), %st +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fadds (%ecx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 faddl (%ecx) +# CHECK-NEXT: - - - 1.00 - - - - faddp %st, %st(1) +# CHECK-NEXT: - - - 1.00 - - - - faddp %st, %st(2) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fiadds (%ecx) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fiaddl (%ecx) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fbld (%ecx) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fbstp (%eax) +# CHECK-NEXT: - - - - - 1.00 - - fchs +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fnclex +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovb %st(1), %st +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovbe %st(1), %st +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmove %st(1), %st +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovnb %st(1), %st +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovnbe %st(1), %st +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovne %st(1), %st +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovnu %st(1), %st +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovu %st(1), %st +# CHECK-NEXT: - - - 1.00 - - - - fcom %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fcom %st(3) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fcoms (%ecx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fcoml (%eax) +# CHECK-NEXT: - - - 1.00 - - - - fcomp %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fcomp %st(3) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fcomps (%ecx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fcompl (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fcompp +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - fcomi %st(3), %st +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - fcompi %st(3), %st +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fcos +# CHECK-NEXT: - - - - - 1.00 - - fdecstp +# CHECK-NEXT: - 14.00 1.00 - - - - - fdiv %st, %st(1) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdiv %st(2), %st +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fdivs (%ecx) +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fdivl (%eax) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdivp %st, %st(1) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdivp %st, %st(2) +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fidivs (%ecx) +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fidivl (%eax) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdivr %st, %st(1) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdivr %st(2), %st +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fdivrs (%ecx) +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fdivrl (%eax) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdivrp %st, %st(1) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdivrp %st, %st(2) +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fidivrs (%ecx) +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fidivrl (%eax) +# CHECK-NEXT: - - - - - 1.00 - - ffree %st(0) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 ficoms (%ecx) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 ficoml (%eax) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 ficomps (%ecx) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 ficompl (%eax) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 filds (%edx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fildl (%ecx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fildll (%eax) +# CHECK-NEXT: - - - - - 1.00 - - fincstp +# CHECK-NEXT: - - 1.00 1.00 - 2.00 - - fninit +# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fists (%edx) +# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fistl (%ecx) +# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fistps (%edx) +# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fistpl (%ecx) +# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fistpll (%eax) +# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 fisttps (%edx) +# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 fisttpl (%ecx) +# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 fisttpll (%eax) +# CHECK-NEXT: - - - - - 1.00 - - fld %st(0) +# CHECK-NEXT: - - 0.50 0.50 - 1.00 0.50 0.50 flds (%edx) +# CHECK-NEXT: - - 0.50 0.50 - 1.00 0.50 0.50 fldl (%ecx) +# CHECK-NEXT: - - 0.50 0.50 - 1.00 0.50 0.50 fldt (%eax) +# CHECK-NEXT: - - - - 1.00 2.00 1.00 1.00 fldcw (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fldenv (%eax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - fld1 +# CHECK-NEXT: - - 1.00 1.00 - - - - fldl2e +# CHECK-NEXT: - - 1.00 1.00 - - - - fldl2t +# CHECK-NEXT: - - 1.00 1.00 - - - - fldlg2 +# CHECK-NEXT: - - 1.00 1.00 - - - - fldln2 +# CHECK-NEXT: - - 1.00 1.00 - - - - fldpi +# CHECK-NEXT: - - - - - 1.00 - - fldz +# CHECK-NEXT: - - 1.00 - - - - - fmul %st, %st(1) +# CHECK-NEXT: - - 1.00 - - - - - fmul %st(2), %st +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fmuls (%ecx) +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fmull (%eax) +# CHECK-NEXT: - - 1.00 - - - - - fmulp %st, %st(1) +# CHECK-NEXT: - - 1.00 - - - - - fmulp %st, %st(2) +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fimuls (%ecx) +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fimull (%eax) +# CHECK-NEXT: - - - - - 1.00 - - fnop +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fpatan +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fprem +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fprem1 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fptan +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - frndint +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - frstor (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fnsave (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fscale +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fsin +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fsincos +# CHECK-NEXT: - 24.00 1.00 - - - - - fsqrt +# CHECK-NEXT: - - - - - 1.00 - - fst %st(0) +# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fsts (%edx) +# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fstl (%ecx) +# CHECK-NEXT: - - - - - 1.00 - - fstp %st(0) +# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fstpl (%edx) +# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fstpl (%ecx) +# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fstpt (%eax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 1.00 fnstcw (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fnstenv (%eax) +# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 1.00 fnstsw (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - frstor (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - wait +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fnsave (%eax) +# CHECK-NEXT: - - - 1.00 - - - - fsub %st, %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fsub %st(2), %st +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fsubs (%ecx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fsubl (%eax) +# CHECK-NEXT: - - - 1.00 - - - - fsubp %st, %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fsubp %st, %st(2) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fisubs (%ecx) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fisubl (%eax) +# CHECK-NEXT: - - - 1.00 - - - - fsubr %st, %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fsubr %st(2), %st +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fsubrs (%ecx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fsubrl (%eax) +# CHECK-NEXT: - - - 1.00 - - - - fsubrp %st, %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fsubrp %st, %st(2) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fisubrs (%ecx) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fisubrl (%eax) +# CHECK-NEXT: - - - 1.00 - - - - ftst +# CHECK-NEXT: - - - 1.00 - - - - fucom %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fucom %st(3) +# CHECK-NEXT: - - - 1.00 - - - - fucomp %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fucomp %st(3) +# CHECK-NEXT: - - - 1.00 - - - - fucompp +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - fucomi %st(3), %st +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - fucompi %st(3), %st +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - wait +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxam +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxch %st(1) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxch %st(3) +# CHECK-NEXT: - - 0.50 0.50 1.00 2.00 0.50 0.50 fxrstor (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxsave (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxtract +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fyl2x +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fyl2xp1 diff --git a/test/tools/llvm-mca/X86/Barcelona/zero-idioms.s b/test/tools/llvm-mca/X86/Barcelona/zero-idioms.s new file mode 100644 index 00000000000..3a14fbc66be --- /dev/null +++ b/test/tools/llvm-mca/X86/Barcelona/zero-idioms.s @@ -0,0 +1,242 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -register-file-stats -iterations=1 < %s | FileCheck %s + +subl %eax, %eax +subq %rax, %rax +xorl %eax, %eax +xorq %rax, %rax + +pcmpgtb %mm2, %mm2 +pcmpgtd %mm2, %mm2 +# pcmpgtq %mm2, %mm2 # invalid operand for instruction +pcmpgtw %mm2, %mm2 + +pcmpgtb %xmm2, %xmm2 +pcmpgtd %xmm2, %xmm2 +pcmpgtq %xmm2, %xmm2 +pcmpgtw %xmm2, %xmm2 + +psubb %mm2, %mm2 +psubd %mm2, %mm2 +psubq %mm2, %mm2 +psubw %mm2, %mm2 +psubb %xmm2, %xmm2 +psubd %xmm2, %xmm2 +psubq %xmm2, %xmm2 +psubw %xmm2, %xmm2 + +psubsb %mm2, %mm2 +psubsw %mm2, %mm2 +psubsb %xmm2, %xmm2 +psubsw %xmm2, %xmm2 + +psubusb %mm2, %mm2 +psubusw %mm2, %mm2 +psubusb %xmm2, %xmm2 +psubusw %xmm2, %xmm2 + +andnps %xmm0, %xmm0 +andnpd %xmm1, %xmm1 + +pandn %mm2, %mm2 +pandn %xmm2, %xmm2 + +xorps %xmm0, %xmm0 +xorpd %xmm1, %xmm1 + +pxor %mm2, %mm2 +pxor %xmm2, %xmm2 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 35 +# CHECK-NEXT: Total Cycles: 39 +# CHECK-NEXT: Total uOps: 35 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.90 +# CHECK-NEXT: IPC: 0.90 +# CHECK-NEXT: Block RThroughput: 11.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 0.25 subl %eax, %eax +# CHECK-NEXT: 1 0 0.25 subq %rax, %rax +# CHECK-NEXT: 1 0 0.25 xorl %eax, %eax +# CHECK-NEXT: 1 0 0.25 xorq %rax, %rax +# CHECK-NEXT: 1 3 1.00 pcmpgtb %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpgtd %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpgtw %mm2, %mm2 +# CHECK-NEXT: 1 0 0.25 pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: 1 3 1.00 psubb %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 psubd %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 psubq %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 psubw %mm2, %mm2 +# CHECK-NEXT: 1 0 0.25 psubb %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 psubd %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 psubq %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 psubw %xmm2, %xmm2 +# CHECK-NEXT: 1 3 1.00 psubsb %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 psubsw %mm2, %mm2 +# CHECK-NEXT: 1 1 0.50 psubsb %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 psubsw %xmm2, %xmm2 +# CHECK-NEXT: 1 3 1.00 psubusb %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 psubusw %mm2, %mm2 +# CHECK-NEXT: 1 1 0.50 psubusb %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 psubusw %xmm2, %xmm2 +# CHECK-NEXT: 1 1 1.00 andnps %xmm0, %xmm0 +# CHECK-NEXT: 1 1 1.00 andnpd %xmm1, %xmm1 +# CHECK-NEXT: 1 1 0.33 pandn %mm2, %mm2 +# CHECK-NEXT: 1 1 0.33 pandn %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 xorps %xmm0, %xmm0 +# CHECK-NEXT: 1 0 0.25 xorpd %xmm1, %xmm1 +# CHECK-NEXT: 1 1 0.33 pxor %mm2, %mm2 +# CHECK-NEXT: 1 0 0.25 pxor %xmm2, %xmm2 + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 39 +# CHECK-NEXT: Max number of mappings used: 30 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 2.00 12.00 - 6.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - - subl %eax, %eax +# CHECK-NEXT: - - - - - - - - subq %rax, %rax +# CHECK-NEXT: - - - - - - - - xorl %eax, %eax +# CHECK-NEXT: - - - - - - - - xorq %rax, %rax +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtb %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtd %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtw %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - psubb %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubd %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubq %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubw %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - psubb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - psubd %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - psubq %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - psubw %xmm2, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - psubsb %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubsw %mm2, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psubsb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - psubsw %xmm2, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - psubusb %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubusw %mm2, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psubusb %xmm2, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - psubusw %xmm2, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - andnps %xmm0, %xmm0 +# CHECK-NEXT: - - - - - 1.00 - - andnpd %xmm1, %xmm1 +# CHECK-NEXT: - - 1.00 - - - - - pandn %mm2, %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pandn %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - xorps %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - - xorpd %xmm1, %xmm1 +# CHECK-NEXT: - - - - - 1.00 - - pxor %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - pxor %xmm2, %xmm2 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 012345678 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DR . . . . . . . . subl %eax, %eax +# CHECK-NEXT: [0,1] DR . . . . . . . . subq %rax, %rax +# CHECK-NEXT: [0,2] DR . . . . . . . . xorl %eax, %eax +# CHECK-NEXT: [0,3] DR . . . . . . . . xorq %rax, %rax +# CHECK-NEXT: [0,4] .DeeeER . . . . . . . pcmpgtb %mm2, %mm2 +# CHECK-NEXT: [0,5] .D===eeeER. . . . . . . pcmpgtd %mm2, %mm2 +# CHECK-NEXT: [0,6] .D======eeeER . . . . . . pcmpgtw %mm2, %mm2 +# CHECK-NEXT: [0,7] .D----------R . . . . . . pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: [0,8] . D---------R . . . . . . pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: [0,9] . D---------R . . . . . . pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: [0,10] . D---------R . . . . . . pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: [0,11] . D========eeeER . . . . . psubb %mm2, %mm2 +# CHECK-NEXT: [0,12] . D==========eeeER . . . . . psubd %mm2, %mm2 +# CHECK-NEXT: [0,13] . D=============eeeER . . . . psubq %mm2, %mm2 +# CHECK-NEXT: [0,14] . D================eeeER. . . . psubw %mm2, %mm2 +# CHECK-NEXT: [0,15] . D--------------------R. . . . psubb %xmm2, %xmm2 +# CHECK-NEXT: [0,16] . D-------------------R. . . . psubd %xmm2, %xmm2 +# CHECK-NEXT: [0,17] . D-------------------R. . . . psubq %xmm2, %xmm2 +# CHECK-NEXT: [0,18] . D-------------------R. . . . psubw %xmm2, %xmm2 +# CHECK-NEXT: [0,19] . D==================eeeER . . . psubsb %mm2, %mm2 +# CHECK-NEXT: [0,20] . D====================eeeER . . psubsw %mm2, %mm2 +# CHECK-NEXT: [0,21] . DeE----------------------R . . psubsb %xmm2, %xmm2 +# CHECK-NEXT: [0,22] . D=eE---------------------R . . psubsw %xmm2, %xmm2 +# CHECK-NEXT: [0,23] . D=======================eeeER . . psubusb %mm2, %mm2 +# CHECK-NEXT: [0,24] . .D=========================eeeER . psubusw %mm2, %mm2 +# CHECK-NEXT: [0,25] . .D=eE--------------------------R . psubusb %xmm2, %xmm2 +# CHECK-NEXT: [0,26] . .D==eE-------------------------R . psubusw %xmm2, %xmm2 +# CHECK-NEXT: [0,27] . .D==eE-------------------------R . andnps %xmm0, %xmm0 +# CHECK-NEXT: [0,28] . . D==eE------------------------R . andnpd %xmm1, %xmm1 +# CHECK-NEXT: [0,29] . . D===========================eER. pandn %mm2, %mm2 +# CHECK-NEXT: [0,30] . . D==eE-------------------------R. pandn %xmm2, %xmm2 +# CHECK-NEXT: [0,31] . . D==E--------------------------R. xorps %xmm0, %xmm0 +# CHECK-NEXT: [0,32] . . D==E-------------------------R. xorpd %xmm1, %xmm1 +# CHECK-NEXT: [0,33] . . D===========================eER pxor %mm2, %mm2 +# CHECK-NEXT: [0,34] . . D==E--------------------------R pxor %xmm2, %xmm2 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 0.0 0.0 0.0 subl %eax, %eax +# CHECK-NEXT: 1. 1 0.0 0.0 0.0 subq %rax, %rax +# CHECK-NEXT: 2. 1 0.0 0.0 0.0 xorl %eax, %eax +# CHECK-NEXT: 3. 1 0.0 0.0 0.0 xorq %rax, %rax +# CHECK-NEXT: 4. 1 1.0 1.0 0.0 pcmpgtb %mm2, %mm2 +# CHECK-NEXT: 5. 1 4.0 0.0 0.0 pcmpgtd %mm2, %mm2 +# CHECK-NEXT: 6. 1 7.0 0.0 0.0 pcmpgtw %mm2, %mm2 +# CHECK-NEXT: 7. 1 0.0 0.0 10.0 pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: 8. 1 0.0 0.0 9.0 pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: 9. 1 0.0 0.0 9.0 pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: 10. 1 0.0 0.0 9.0 pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: 11. 1 9.0 0.0 0.0 psubb %mm2, %mm2 +# CHECK-NEXT: 12. 1 11.0 0.0 0.0 psubd %mm2, %mm2 +# CHECK-NEXT: 13. 1 14.0 0.0 0.0 psubq %mm2, %mm2 +# CHECK-NEXT: 14. 1 17.0 0.0 0.0 psubw %mm2, %mm2 +# CHECK-NEXT: 15. 1 0.0 0.0 20.0 psubb %xmm2, %xmm2 +# CHECK-NEXT: 16. 1 0.0 0.0 19.0 psubd %xmm2, %xmm2 +# CHECK-NEXT: 17. 1 0.0 0.0 19.0 psubq %xmm2, %xmm2 +# CHECK-NEXT: 18. 1 0.0 0.0 19.0 psubw %xmm2, %xmm2 +# CHECK-NEXT: 19. 1 19.0 0.0 0.0 psubsb %mm2, %mm2 +# CHECK-NEXT: 20. 1 21.0 0.0 0.0 psubsw %mm2, %mm2 +# CHECK-NEXT: 21. 1 1.0 1.0 22.0 psubsb %xmm2, %xmm2 +# CHECK-NEXT: 22. 1 2.0 0.0 21.0 psubsw %xmm2, %xmm2 +# CHECK-NEXT: 23. 1 24.0 0.0 0.0 psubusb %mm2, %mm2 +# CHECK-NEXT: 24. 1 26.0 0.0 0.0 psubusw %mm2, %mm2 +# CHECK-NEXT: 25. 1 2.0 0.0 26.0 psubusb %xmm2, %xmm2 +# CHECK-NEXT: 26. 1 3.0 0.0 25.0 psubusw %xmm2, %xmm2 +# CHECK-NEXT: 27. 1 3.0 3.0 25.0 andnps %xmm0, %xmm0 +# CHECK-NEXT: 28. 1 3.0 3.0 24.0 andnpd %xmm1, %xmm1 +# CHECK-NEXT: 29. 1 28.0 0.0 0.0 pandn %mm2, %mm2 +# CHECK-NEXT: 30. 1 3.0 0.0 25.0 pandn %xmm2, %xmm2 +# CHECK-NEXT: 31. 1 3.0 0.0 26.0 xorps %xmm0, %xmm0 +# CHECK-NEXT: 32. 1 3.0 0.0 25.0 xorpd %xmm1, %xmm1 +# CHECK-NEXT: 33. 1 28.0 0.0 0.0 pxor %mm2, %mm2 +# CHECK-NEXT: 34. 1 3.0 0.0 26.0 pxor %xmm2, %xmm2 diff --git a/test/tools/llvm-mca/X86/cpus.s b/test/tools/llvm-mca/X86/cpus.s index f5bb1d92cf5..e90abf85d07 100644 --- a/test/tools/llvm-mca/X86/cpus.s +++ b/test/tools/llvm-mca/X86/cpus.s @@ -1,4 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=BARCELONA %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=BDVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=BTVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=ZNVER1 %s @@ -18,6 +19,11 @@ add %edi, %eax # ALL-NEXT: Total Cycles: 103 # ALL-NEXT: Total uOps: 100 +# BARCELONA: Dispatch Width: 4 +# BARCELONA-NEXT: uOps Per Cycle: 0.97 +# BARCELONA-NEXT: IPC: 0.97 +# BARCELONA-NEXT: Block RThroughput: 0.3 + # BDVER2: Dispatch Width: 4 # BDVER2-NEXT: uOps Per Cycle: 0.97 # BDVER2-NEXT: IPC: 0.97 diff --git a/test/tools/llvm-mca/X86/read-after-ld-1.s b/test/tools/llvm-mca/X86/read-after-ld-1.s index 44f6b769733..f3a88431aa0 100644 --- a/test/tools/llvm-mca/X86/read-after-ld-1.s +++ b/test/tools/llvm-mca/X86/read-after-ld-1.s @@ -3,6 +3,7 @@ # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=HASWELL # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDWELL # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=SKYLAKE +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BARCELONA # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BTVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER1 @@ -10,122 +11,137 @@ vdivps %xmm0, %xmm1, %xmm1 vaddps (%rax), %xmm1, %xmm1 -# ALL: Iterations: 1 -# ALL-NEXT: Instructions: 2 +# ALL: Iterations: 1 +# ALL-NEXT: Instructions: 2 -# BDVER2-NEXT: Total Cycles: 17 -# BDVER2-NEXT: Total uOps: 2 +# BARCELONA-NEXT: Total Cycles: 20 +# BARCELONA-NEXT: Total uOps: 3 -# BDWELL-NEXT: Total Cycles: 17 -# BDWELL-NEXT: Total uOps: 3 +# BDVER2-NEXT: Total Cycles: 17 +# BDVER2-NEXT: Total uOps: 2 -# BTVER2-NEXT: Total Cycles: 25 -# BTVER2-NEXT: Total uOps: 2 +# BDWELL-NEXT: Total Cycles: 17 +# BDWELL-NEXT: Total uOps: 3 -# HASWELL-NEXT: Total Cycles: 19 -# HASWELL-NEXT: Total uOps: 3 +# BTVER2-NEXT: Total Cycles: 25 +# BTVER2-NEXT: Total uOps: 2 -# SANDY-NEXT: Total Cycles: 20 -# SANDY-NEXT: Total uOps: 3 +# HASWELL-NEXT: Total Cycles: 19 +# HASWELL-NEXT: Total uOps: 3 -# SKYLAKE-NEXT: Total Cycles: 18 -# SKYLAKE-NEXT: Total uOps: 3 +# SANDY-NEXT: Total Cycles: 20 +# SANDY-NEXT: Total uOps: 3 -# ZNVER1-NEXT: Total Cycles: 20 -# ZNVER1-NEXT: Total uOps: 2 +# SKYLAKE-NEXT: Total Cycles: 18 +# SKYLAKE-NEXT: Total uOps: 3 -# BDVER2: Dispatch Width: 4 -# BDVER2-NEXT: uOps Per Cycle: 0.12 -# BDVER2-NEXT: IPC: 0.12 -# BDVER2-NEXT: Block RThroughput: 5.0 +# ZNVER1-NEXT: Total Cycles: 20 +# ZNVER1-NEXT: Total uOps: 2 -# BDWELL: Dispatch Width: 4 -# BDWELL-NEXT: uOps Per Cycle: 0.18 -# BDWELL-NEXT: IPC: 0.12 -# BDWELL-NEXT: Block RThroughput: 5.0 +# BARCELONA: Dispatch Width: 4 +# BARCELONA-NEXT: uOps Per Cycle: 0.15 +# BARCELONA-NEXT: IPC: 0.10 +# BARCELONA-NEXT: Block RThroughput: 14.0 -# BTVER2: Dispatch Width: 2 -# BTVER2-NEXT: uOps Per Cycle: 0.08 -# BTVER2-NEXT: IPC: 0.08 -# BTVER2-NEXT: Block RThroughput: 19.0 +# BDVER2: Dispatch Width: 4 +# BDVER2-NEXT: uOps Per Cycle: 0.12 +# BDVER2-NEXT: IPC: 0.12 +# BDVER2-NEXT: Block RThroughput: 5.0 -# HASWELL: Dispatch Width: 4 -# HASWELL-NEXT: uOps Per Cycle: 0.16 -# HASWELL-NEXT: IPC: 0.11 -# HASWELL-NEXT: Block RThroughput: 7.0 +# BDWELL: Dispatch Width: 4 +# BDWELL-NEXT: uOps Per Cycle: 0.18 +# BDWELL-NEXT: IPC: 0.12 +# BDWELL-NEXT: Block RThroughput: 5.0 -# SANDY: Dispatch Width: 4 -# SANDY-NEXT: uOps Per Cycle: 0.15 -# SANDY-NEXT: IPC: 0.10 -# SANDY-NEXT: Block RThroughput: 14.0 +# BTVER2: Dispatch Width: 2 +# BTVER2-NEXT: uOps Per Cycle: 0.08 +# BTVER2-NEXT: IPC: 0.08 +# BTVER2-NEXT: Block RThroughput: 19.0 -# SKYLAKE: Dispatch Width: 6 -# SKYLAKE-NEXT: uOps Per Cycle: 0.17 -# SKYLAKE-NEXT: IPC: 0.11 -# SKYLAKE-NEXT: Block RThroughput: 3.0 +# HASWELL: Dispatch Width: 4 +# HASWELL-NEXT: uOps Per Cycle: 0.16 +# HASWELL-NEXT: IPC: 0.11 +# HASWELL-NEXT: Block RThroughput: 7.0 -# ZNVER1: Dispatch Width: 4 -# ZNVER1-NEXT: uOps Per Cycle: 0.10 -# ZNVER1-NEXT: IPC: 0.10 -# ZNVER1-NEXT: Block RThroughput: 1.0 +# SANDY: Dispatch Width: 4 +# SANDY-NEXT: uOps Per Cycle: 0.15 +# SANDY-NEXT: IPC: 0.10 +# SANDY-NEXT: Block RThroughput: 14.0 -# ALL: Timeline view: +# SKYLAKE: Dispatch Width: 6 +# SKYLAKE-NEXT: uOps Per Cycle: 0.17 +# SKYLAKE-NEXT: IPC: 0.11 +# SKYLAKE-NEXT: Block RThroughput: 3.0 -# BDVER2-NEXT: 0123456 -# BDVER2-NEXT: Index 0123456789 +# ZNVER1: Dispatch Width: 4 +# ZNVER1-NEXT: uOps Per Cycle: 0.10 +# ZNVER1-NEXT: IPC: 0.10 +# ZNVER1-NEXT: Block RThroughput: 1.0 -# BDWELL-NEXT: 0123456 -# BDWELL-NEXT: Index 0123456789 +# ALL: Timeline view: -# BTVER2-NEXT: 0123456789 -# BTVER2-NEXT: Index 0123456789 01234 +# BARCELONA-NEXT: 0123456789 +# BARCELONA-NEXT: Index 0123456789 -# HASWELL-NEXT: 012345678 -# HASWELL-NEXT: Index 0123456789 +# BDVER2-NEXT: 0123456 +# BDVER2-NEXT: Index 0123456789 -# SANDY-NEXT: 0123456789 -# SANDY-NEXT: Index 0123456789 +# BDWELL-NEXT: 0123456 +# BDWELL-NEXT: Index 0123456789 -# SKYLAKE-NEXT: 01234567 -# SKYLAKE-NEXT: Index 0123456789 +# BTVER2-NEXT: 0123456789 +# BTVER2-NEXT: Index 0123456789 01234 -# ZNVER1-NEXT: 0123456789 -# ZNVER1-NEXT: Index 0123456789 +# HASWELL-NEXT: 012345678 +# HASWELL-NEXT: Index 0123456789 -# BDVER2: [0,0] DeeeeeeeeeER .. vdivps %xmm0, %xmm1, %xmm1 -# BDVER2-NEXT: [0,1] D====eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 +# SANDY-NEXT: 0123456789 +# SANDY-NEXT: Index 0123456789 -# BDWELL: [0,0] DeeeeeeeeeeeER .. vdivps %xmm0, %xmm1, %xmm1 -# BDWELL-NEXT: [0,1] D======eeeeeeeeER vaddps (%rax), %xmm1, %xmm1 +# SKYLAKE-NEXT: 01234567 +# SKYLAKE-NEXT: Index 0123456789 -# BTVER2: [0,0] DeeeeeeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1 -# BTVER2-NEXT: [0,1] D==============eeeeeeeeER vaddps (%rax), %xmm1, %xmm1 +# ZNVER1-NEXT: 0123456789 +# ZNVER1-NEXT: Index 0123456789 -# HASWELL: [0,0] DeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1 -# HASWELL-NEXT: [0,1] D=======eeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 +# BARCELONA: [0,0] DeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1 +# BARCELONA-NEXT: [0,1] D========eeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 -# SANDY: [0,0] DeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1 -# SANDY-NEXT: [0,1] D========eeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 +# BDVER2: [0,0] DeeeeeeeeeER .. vdivps %xmm0, %xmm1, %xmm1 +# BDVER2-NEXT: [0,1] D====eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 -# SKYLAKE: [0,0] DeeeeeeeeeeeER . . vdivps %xmm0, %xmm1, %xmm1 -# SKYLAKE-NEXT: [0,1] D=====eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 +# BDWELL: [0,0] DeeeeeeeeeeeER .. vdivps %xmm0, %xmm1, %xmm1 +# BDWELL-NEXT: [0,1] D======eeeeeeeeER vaddps (%rax), %xmm1, %xmm1 -# ZNVER1: [0,0] DeeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1 -# ZNVER1-NEXT: [0,1] D=======eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 +# BTVER2: [0,0] DeeeeeeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1 +# BTVER2-NEXT: [0,1] D==============eeeeeeeeER vaddps (%rax), %xmm1, %xmm1 -# ALL: Average Wait times (based on the timeline view): -# ALL-NEXT: [0]: Executions -# ALL-NEXT: [1]: Average time spent waiting in a scheduler's queue -# ALL-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready -# ALL-NEXT: [3]: Average time elapsed from WB until retire stage +# HASWELL: [0,0] DeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1 +# HASWELL-NEXT: [0,1] D=======eeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 -# ALL: [0] [1] [2] [3] -# ALL-NEXT: 0. 1 1.0 1.0 0.0 vdivps %xmm0, %xmm1, %xmm1 +# SANDY: [0,0] DeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1 +# SANDY-NEXT: [0,1] D========eeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 -# BDVER2-NEXT: 1. 1 5.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 -# BDWELL-NEXT: 1. 1 7.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 -# BTVER2-NEXT: 1. 1 15.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 -# HASWELL-NEXT: 1. 1 8.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 -# SANDY-NEXT: 1. 1 9.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 -# SKYLAKE-NEXT: 1. 1 6.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 -# ZNVER1-NEXT: 1. 1 8.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 +# SKYLAKE: [0,0] DeeeeeeeeeeeER . . vdivps %xmm0, %xmm1, %xmm1 +# SKYLAKE-NEXT: [0,1] D=====eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 + +# ZNVER1: [0,0] DeeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1 +# ZNVER1-NEXT: [0,1] D=======eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 + +# ALL: Average Wait times (based on the timeline view): +# ALL-NEXT: [0]: Executions +# ALL-NEXT: [1]: Average time spent waiting in a scheduler's queue +# ALL-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# ALL-NEXT: [3]: Average time elapsed from WB until retire stage + +# ALL: [0] [1] [2] [3] +# ALL-NEXT: 0. 1 1.0 1.0 0.0 vdivps %xmm0, %xmm1, %xmm1 + +# BARCELONA-NEXT: 1. 1 9.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 +# BDVER2-NEXT: 1. 1 5.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 +# BDWELL-NEXT: 1. 1 7.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 +# BTVER2-NEXT: 1. 1 15.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 +# HASWELL-NEXT: 1. 1 8.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 +# SANDY-NEXT: 1. 1 9.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 +# SKYLAKE-NEXT: 1. 1 6.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 +# ZNVER1-NEXT: 1. 1 8.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 diff --git a/test/tools/llvm-mca/X86/register-file-statistics.s b/test/tools/llvm-mca/X86/register-file-statistics.s index cf847abe516..685433ae162 100644 --- a/test/tools/llvm-mca/X86/register-file-statistics.s +++ b/test/tools/llvm-mca/X86/register-file-statistics.s @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL %s +# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=BARCELONA %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,BDVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,BTVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,ZNVER1 %s @@ -14,36 +15,40 @@ xor %eax, %ebx -# ALL: Register File statistics: -# ALL-NEXT: Total number of mappings created: 2 -# ALL-NEXT: Max number of mappings used: 2 - -# BDVER2: * Register File #1 -- PdFpuPRF: -# BDVER2-NEXT: Number of physical registers: 160 -# BDVER2-NEXT: Total number of mappings created: 0 -# BDVER2-NEXT: Max number of mappings used: 0 - -# BTVER2: * Register File #1 -- JFpuPRF: -# BTVER2-NEXT: Number of physical registers: 72 -# BTVER2-NEXT: Total number of mappings created: 0 -# BTVER2-NEXT: Max number of mappings used: 0 - -# ZNVER1: * Register File #1 -- ZnFpuPRF: -# ZNVER1-NEXT: Number of physical registers: 160 -# ZNVER1-NEXT: Total number of mappings created: 0 -# ZNVER1-NEXT: Max number of mappings used: 0 - -# BDVER2: * Register File #2 -- PdIntegerPRF: -# BDVER2-NEXT: Number of physical registers: 96 -# BDVER2-NEXT: Total number of mappings created: 2 -# BDVER2-NEXT: Max number of mappings used: 2 - -# BTVER2: * Register File #2 -- JIntegerPRF: -# BTVER2-NEXT: Number of physical registers: 64 -# BTVER2-NEXT: Total number of mappings created: 2 -# BTVER2-NEXT: Max number of mappings used: 2 - -# ZNVER1: * Register File #2 -- ZnIntegerPRF: -# ZNVER1-NEXT: Number of physical registers: 168 -# ZNVER1-NEXT: Total number of mappings created: 2 -# ZNVER1-NEXT: Max number of mappings used: 2 +# ALL: Register File statistics: +# ALL-NEXT: Total number of mappings created: 2 +# ALL-NEXT: Max number of mappings used: 2 + +# BARCELONA: Register File statistics: +# BARCELONA-NEXT: Total number of mappings created: 2 +# BARCELONA-NEXT: Max number of mappings used: 2 + +# BDVER2: * Register File #1 -- PdFpuPRF: +# BDVER2-NEXT: Number of physical registers: 160 +# BDVER2-NEXT: Total number of mappings created: 0 +# BDVER2-NEXT: Max number of mappings used: 0 + +# BTVER2: * Register File #1 -- JFpuPRF: +# BTVER2-NEXT: Number of physical registers: 72 +# BTVER2-NEXT: Total number of mappings created: 0 +# BTVER2-NEXT: Max number of mappings used: 0 + +# ZNVER1: * Register File #1 -- ZnFpuPRF: +# ZNVER1-NEXT: Number of physical registers: 160 +# ZNVER1-NEXT: Total number of mappings created: 0 +# ZNVER1-NEXT: Max number of mappings used: 0 + +# BDVER2: * Register File #2 -- PdIntegerPRF: +# BDVER2-NEXT: Number of physical registers: 96 +# BDVER2-NEXT: Total number of mappings created: 2 +# BDVER2-NEXT: Max number of mappings used: 2 + +# BTVER2: * Register File #2 -- JIntegerPRF: +# BTVER2-NEXT: Number of physical registers: 64 +# BTVER2-NEXT: Total number of mappings created: 2 +# BTVER2-NEXT: Max number of mappings used: 2 + +# ZNVER1: * Register File #2 -- ZnIntegerPRF: +# ZNVER1-NEXT: Number of physical registers: 168 +# ZNVER1-NEXT: Total number of mappings created: 2 +# ZNVER1-NEXT: Max number of mappings used: 2 diff --git a/test/tools/llvm-mca/X86/scheduler-queue-usage.s b/test/tools/llvm-mca/X86/scheduler-queue-usage.s index 733745a093d..8cb1a506bed 100644 --- a/test/tools/llvm-mca/X86/scheduler-queue-usage.s +++ b/test/tools/llvm-mca/X86/scheduler-queue-usage.s @@ -1,4 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BARCELONA %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BDVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BTVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,ZNVER1 %s @@ -18,6 +19,12 @@ xor %eax, %ebx # ALL-NEXT: 0, 3 (75.0%) # ALL-NEXT: 1, 1 (25.0%) +# BARCELONA: Scheduler's queue usage: +# BARCELONA-NEXT: [1] Resource name. +# BARCELONA-NEXT: [2] Average number of used buffer entries. +# BARCELONA-NEXT: [3] Maximum number of used buffer entries. +# BARCELONA-NEXT: [4] Total number of buffer entries. + # BDVER2: Scheduler's queue usage: # BDVER2-NEXT: [1] Resource name. # BDVER2-NEXT: [2] Average number of used buffer entries. @@ -81,6 +88,9 @@ xor %eax, %ebx # ZNVER1-NEXT: [3] Maximum number of used buffer entries. # ZNVER1-NEXT: [4] Total number of buffer entries. +# BARCELONA: [1] [2] [3] [4] +# BARCELONA-NEXT: SBPortAny 0 1 54 + # BDVER2: [1] [2] [3] [4] # BDVER2-NEXT: PdEX 0 1 40 # BDVER2-NEXT: PdFPU 0 0 64 diff --git a/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s b/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s index aa1bc886c10..a4b3f561e5d 100644 --- a/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s +++ b/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s @@ -1,4 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BARCELONA # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BTVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER1 @@ -30,6 +31,9 @@ rcpss (%rax), %xmm1 # ALL: Timeline view: +# BARCELONA-NEXT: 0123456789 +# BARCELONA-NEXT: Index 0123456789 0123 + # BDVER2-NEXT: 01234567 # BDVER2-NEXT: Index 0123456789 @@ -48,6 +52,9 @@ rcpss (%rax), %xmm1 # ZNVER1-NEXT: 0123456789 0 # ZNVER1-NEXT: Index 0123456789 0123456789 +# BARCELONA: [0,0] DeER . . . . . leaq 8(%rsp,%rdi,2), %rax +# BARCELONA-NEXT: [0,1] D=eeeeeeeeeeeeeeeeeeeeER sqrtss (%rax), %xmm1 + # BDVER2: [0,0] DeER . . . . leaq 8(%rsp,%rdi,2), %rax # BDVER2-NEXT: [0,1] D=eeeeeeeeeeeeeeER sqrtss (%rax), %xmm1 @@ -75,6 +82,7 @@ rcpss (%rax), %xmm1 # ALL: [0] [1] [2] [3] # ALL-NEXT: 0. 1 1.0 1.0 0.0 leaq 8(%rsp,%rdi,2), %rax +# BARCELONA-NEXT: 1. 1 2.0 0.0 0.0 sqrtss (%rax), %xmm1 # BDVER2-NEXT: 1. 1 2.0 0.0 0.0 sqrtss (%rax), %xmm1 # BROADWELL-NEXT: 1. 1 2.0 0.0 0.0 sqrtss (%rax), %xmm1 # BTVER2-NEXT: 1. 1 3.0 0.0 0.0 sqrtss (%rax), %xmm1 @@ -86,6 +94,9 @@ rcpss (%rax), %xmm1 # ALL: Timeline view: +# BARCELONA-NEXT: 0123456789 0 +# BARCELONA-NEXT: Index 0123456789 0123456789 + # BDVER2-NEXT: 01234567 # BDVER2-NEXT: Index 0123456789 @@ -104,6 +115,9 @@ rcpss (%rax), %xmm1 # ZNVER1-NEXT: 0123456789 0 # ZNVER1-NEXT: Index 0123456789 0123456789 +# BARCELONA: [0,0] DeER . . . . . . leaq 8(%rsp,%rdi,2), %rax +# BARCELONA-NEXT: [0,1] D=eeeeeeeeeeeeeeeeeeeeeeeeeeeER sqrtsd (%rax), %xmm1 + # BDVER2: [0,0] DeER . . . . leaq 8(%rsp,%rdi,2), %rax # BDVER2-NEXT: [0,1] D=eeeeeeeeeeeeeeER sqrtsd (%rax), %xmm1 @@ -131,6 +145,7 @@ rcpss (%rax), %xmm1 # ALL: [0] [1] [2] [3] # ALL-NEXT: 0. 1 1.0 1.0 0.0 leaq 8(%rsp,%rdi,2), %rax +# BARCELONA-NEXT: 1. 1 2.0 0.0 0.0 sqrtsd (%rax), %xmm1 # BDVER2-NEXT: 1. 1 2.0 0.0 0.0 sqrtsd (%rax), %xmm1 # BROADWELL-NEXT: 1. 1 2.0 0.0 0.0 sqrtsd (%rax), %xmm1 # BTVER2-NEXT: 1. 1 3.0 0.0 0.0 sqrtsd (%rax), %xmm1 @@ -142,6 +157,7 @@ rcpss (%rax), %xmm1 # ALL: Timeline view: +# BARCELONA-NEXT: 01234 # BDVER2-NEXT: 0123 # BROADWELL-NEXT: 0123 # BTVER2-NEXT: 01 @@ -151,6 +167,9 @@ rcpss (%rax), %xmm1 # ALL-NEXT: Index 0123456789 +# BARCELONA: [0,0] DeER . . . leaq 8(%rsp,%rdi,2), %rax +# BARCELONA-NEXT: [0,1] D=eeeeeeeeeeeER rsqrtss (%rax), %xmm1 + # BDVER2: [0,0] DeER . . . leaq 8(%rsp,%rdi,2), %rax # BDVER2-NEXT: [0,1] D=eeeeeeeeeeER rsqrtss (%rax), %xmm1 @@ -178,6 +197,7 @@ rcpss (%rax), %xmm1 # ALL: [0] [1] [2] [3] # ALL-NEXT: 0. 1 1.0 1.0 0.0 leaq 8(%rsp,%rdi,2), %rax +# BARCELONA-NEXT: 1. 1 2.0 0.0 0.0 rsqrtss (%rax), %xmm1 # BDVER2-NEXT: 1. 1 2.0 0.0 0.0 rsqrtss (%rax), %xmm1 # BROADWELL-NEXT: 1. 1 2.0 0.0 0.0 rsqrtss (%rax), %xmm1 # BTVER2-NEXT: 1. 1 3.0 0.0 0.0 rsqrtss (%rax), %xmm1 @@ -189,6 +209,7 @@ rcpss (%rax), %xmm1 # ALL: Timeline view: +# BARCELONA-NEXT: 01234 # BDVER2-NEXT: 0123 # BROADWELL-NEXT: 0123 # BTVER2-NEXT: 01 @@ -198,6 +219,9 @@ rcpss (%rax), %xmm1 # ALL-NEXT: Index 0123456789 +# BARCELONA: [0,0] DeER . . . leaq 8(%rsp,%rdi,2), %rax +# BARCELONA-NEXT: [0,1] D=eeeeeeeeeeeER rcpss (%rax), %xmm1 + # BDVER2: [0,0] DeER . . . leaq 8(%rsp,%rdi,2), %rax # BDVER2-NEXT: [0,1] D=eeeeeeeeeeER rcpss (%rax), %xmm1 @@ -225,6 +249,7 @@ rcpss (%rax), %xmm1 # ALL: [0] [1] [2] [3] # ALL-NEXT: 0. 1 1.0 1.0 0.0 leaq 8(%rsp,%rdi,2), %rax +# BARCELONA-NEXT: 1. 1 2.0 0.0 0.0 rcpss (%rax), %xmm1 # BDVER2-NEXT: 1. 1 2.0 0.0 0.0 rcpss (%rax), %xmm1 # BROADWELL-NEXT: 1. 1 2.0 0.0 0.0 rcpss (%rax), %xmm1 # BTVER2-NEXT: 1. 1 3.0 0.0 0.0 rcpss (%rax), %xmm1 -- 2.40.0