From faff8226b0ad2dea100529bf49cae3f6c9b7a32d Mon Sep 17 00:00:00 2001 From: Eugene Zelenko Date: Wed, 1 Feb 2017 22:56:06 +0000 Subject: [PATCH] [AArch64] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293836 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64CallLowering.cpp | 36 ++++++++++++----- lib/Target/AArch64/AArch64CallLowering.h | 18 +++++---- .../AArch64/AArch64RegisterBankInfo.cpp | 39 ++++++++++--------- 3 files changed, 59 insertions(+), 34 deletions(-) diff --git a/lib/Target/AArch64/AArch64CallLowering.cpp b/lib/Target/AArch64/AArch64CallLowering.cpp index 4f5b2886b1a..c8a3ce5463e 100644 --- a/lib/Target/AArch64/AArch64CallLowering.cpp +++ b/lib/Target/AArch64/AArch64CallLowering.cpp @@ -1,4 +1,4 @@ -//===-- llvm/lib/Target/AArch64/AArch64CallLowering.cpp - Call lowering ---===// +//===--- AArch64CallLowering.cpp - Call lowering --------------------------===// // // The LLVM Compiler Infrastructure // @@ -15,15 +15,34 @@ #include "AArch64CallLowering.h" #include "AArch64ISelLowering.h" - +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/Analysis.h" +#include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" -#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" #include "llvm/CodeGen/GlobalISel/Utils.h" +#include "llvm/CodeGen/LowLevelType.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/MachineValueType.h" +#include "llvm/CodeGen/ValueTypes.h" +#include "llvm/IR/Argument.h" +#include "llvm/IR/Attributes.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/Type.h" +#include "llvm/IR/Value.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" +#include +#include +#include +#include + using namespace llvm; #ifndef LLVM_BUILD_GLOBAL_ISEL @@ -31,8 +50,7 @@ using namespace llvm; #endif AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI) - : CallLowering(&TLI) { -} + : CallLowering(&TLI) {} struct IncomingArgHandler : public CallLowering::ValueHandler { IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, @@ -131,10 +149,10 @@ struct OutgoingArgHandler : public CallLowering::ValueHandler { MIRBuilder.buildStore(ValVReg, Addr, *MMO); } - virtual bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT, - CCValAssign::LocInfo LocInfo, - const CallLowering::ArgInfo &Info, - CCState &State) override { + bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + const CallLowering::ArgInfo &Info, + CCState &State) override { if (Info.IsFixed) return AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State); return AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State); diff --git a/lib/Target/AArch64/AArch64CallLowering.h b/lib/Target/AArch64/AArch64CallLowering.h index d1453d0071f..23c529ac139 100644 --- a/lib/Target/AArch64/AArch64CallLowering.h +++ b/lib/Target/AArch64/AArch64CallLowering.h @@ -1,4 +1,4 @@ -//===-- llvm/lib/Target/AArch64/AArch64CallLowering.h - Call lowering -----===// +//===--- AArch64CallLowering.h - Call lowering ------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -12,18 +12,20 @@ /// //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64CALLLOWERING -#define LLVM_LIB_TARGET_AARCH64_AARCH64CALLLOWERING +#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64CALLLOWERING_H +#define LLVM_LIB_TARGET_AARCH64_AARCH64CALLLOWERING_H +#include "llvm/ADT/ArrayRef.h" #include "llvm/CodeGen/GlobalISel/CallLowering.h" -#include "llvm/CodeGen/ValueTypes.h" +#include +#include namespace llvm { class AArch64TargetLowering; class AArch64CallLowering: public CallLowering { - public: +public: AArch64CallLowering(const AArch64TargetLowering &TLI); bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, @@ -52,5 +54,7 @@ private: const DataLayout &DL, MachineRegisterInfo &MRI, const SplitArgTy &SplitArg) const; }; -} // End of namespace llvm; -#endif + +} // end namespace llvm + +#endif // LLVM_LIB_TARGET_AARCH64_AARCH64CALLLOWERING_H diff --git a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index 2568f11bd24..de04d343c23 100644 --- a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -1,4 +1,4 @@ -//===- AArch64RegisterBankInfo.cpp -------------------------------*- C++ -*-==// +//===- AArch64RegisterBankInfo.cpp ----------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -13,13 +13,21 @@ //===----------------------------------------------------------------------===// #include "AArch64RegisterBankInfo.h" -#include "AArch64InstrInfo.h" // For XXXRegClassID. +#include "AArch64InstrInfo.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/LowLevelType.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/GlobalISel/RegisterBank.h" #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Target/TargetOpcodes.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" +#include +#include #define GET_TARGET_REGBANK_IMPL #include "AArch64GenRegisterBank.inc" @@ -95,7 +103,7 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) assert( \ checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \ #Idx " is incorrectly initialized"); \ - } while (0) + } while (false) CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR); CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR); @@ -112,7 +120,7 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) PartialMappingIdx::PMI_First##RBName, Size, \ Offset) && \ #RBName #Size " " #Offset " is incorrectly initialized"); \ - } while (0) + } while (false) #define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0) @@ -131,7 +139,7 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) CHECK_VALUEMAP_IMPL(RBName, Size, 0); \ CHECK_VALUEMAP_IMPL(RBName, Size, 1); \ CHECK_VALUEMAP_IMPL(RBName, Size, 2); \ - } while (0) + } while (false) CHECK_VALUEMAP_3OPS(GPR, 32); CHECK_VALUEMAP_3OPS(GPR, 64); @@ -159,7 +167,7 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) Map[1].NumBreakDowns == 1 && #RBNameSrc #Size \ " Src is incorrectly initialized"); \ \ - } while (0) + } while (false) CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 32); CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 32); @@ -338,13 +346,12 @@ void AArch64RegisterBankInfo::applyMappingImpl( switch (OpdMapper.getMI().getOpcode()) { case TargetOpcode::G_OR: case TargetOpcode::G_BITCAST: - case TargetOpcode::G_LOAD: { + case TargetOpcode::G_LOAD: // Those ID must match getInstrAlternativeMappings. assert((OpdMapper.getInstrMapping().getID() >= 1 && OpdMapper.getInstrMapping().getID() <= 4) && "Don't know how to handle that ID"); return applyDefaultMapping(OpdMapper); - } default: llvm_unreachable("Don't know how to handle that operation"); } @@ -494,21 +501,18 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // fine-tune the computed mapping. switch (Opc) { case TargetOpcode::G_SITOFP: - case TargetOpcode::G_UITOFP: { + case TargetOpcode::G_UITOFP: OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR}; break; - } case TargetOpcode::G_FPTOSI: - case TargetOpcode::G_FPTOUI: { + case TargetOpcode::G_FPTOUI: OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR}; break; - } - case TargetOpcode::G_FCMP: { + case TargetOpcode::G_FCMP: OpRegBankIdx = {PMI_FirstGPR, /* Predicate */ PMI_None, PMI_FirstFPR, PMI_FirstFPR}; break; - } - case TargetOpcode::G_BITCAST: { + case TargetOpcode::G_BITCAST: // This is going to be a cross register bank copy and this is expensive. if (OpRegBankIdx[0] != OpRegBankIdx[1]) Cost = copyCost( @@ -516,8 +520,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[1]].RegBank, OpSize[0]); break; - } - case TargetOpcode::G_LOAD: { + case TargetOpcode::G_LOAD: // Loading in vector unit is slightly more expensive. // This is actually only true for the LD1R and co instructions, // but anyway for the fast mode this number does not matter and @@ -526,7 +529,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // FIXME: Should be derived from the scheduling model. if (OpRegBankIdx[0] >= PMI_FirstFPR) Cost = 2; - } + break; } // Finally construct the computed mapping. -- 2.50.1