From fac43a31235db3a52317b060d64cf396f1761cad Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Fri, 27 Jul 2018 18:12:29 +0000
Subject: [PATCH] [AArch64, PowerPC, x86] add more signbit math tests; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338143 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/AArch64/signbit-shift.ll | 23 ++++++++++++++++++++++
 test/CodeGen/PowerPC/signbit-shift.ll | 28 +++++++++++++++++++++++++++
 test/CodeGen/X86/signbit-shift.ll     | 25 ++++++++++++++++++++++++
 3 files changed, 76 insertions(+)

diff --git a/test/CodeGen/AArch64/signbit-shift.ll b/test/CodeGen/AArch64/signbit-shift.ll
index 521a0b8c149..c2f62c24026 100644
--- a/test/CodeGen/AArch64/signbit-shift.ll
+++ b/test/CodeGen/AArch64/signbit-shift.ll
@@ -222,3 +222,26 @@ define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
+define i32 @sub_lshr(i32 %x) {
+; CHECK-LABEL: sub_lshr:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #43
+; CHECK-NEXT:    sub w0, w8, w0, lsr #31
+; CHECK-NEXT:    ret
+  %sh = lshr i32 %x, 31
+  %r = sub i32 43, %sh
+  ret i32 %r
+}
+
+define <4 x i32> @sub_lshr_vec_splat(<4 x i32> %x) {
+; CHECK-LABEL: sub_lshr_vec_splat:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushr v0.4s, v0.4s, #31
+; CHECK-NEXT:    movi v1.4s, #42
+; CHECK-NEXT:    sub v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    ret
+  %e = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+  %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
+  ret <4 x i32> %r
+}
+
diff --git a/test/CodeGen/PowerPC/signbit-shift.ll b/test/CodeGen/PowerPC/signbit-shift.ll
index 7bc9cef9590..d82fe842b03 100644
--- a/test/CodeGen/PowerPC/signbit-shift.ll
+++ b/test/CodeGen/PowerPC/signbit-shift.ll
@@ -240,3 +240,31 @@ define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
+define i32 @sub_lshr(i32 %x) {
+; CHECK-LABEL: sub_lshr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    subfic 3, 3, 43
+; CHECK-NEXT:    blr
+  %sh = lshr i32 %x, 31
+  %r = sub i32 43, %sh
+  ret i32 %r
+}
+
+define <4 x i32> @sub_lshr_vec_splat(<4 x i32> %x) {
+; CHECK-LABEL: sub_lshr_vec_splat:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltisw 3, -16
+; CHECK-NEXT:    vspltisw 4, 15
+; CHECK-NEXT:    addis 3, 2, .LCPI19_0@toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI19_0@toc@l
+; CHECK-NEXT:    vsubuwm 3, 4, 3
+; CHECK-NEXT:    vsrw 2, 2, 3
+; CHECK-NEXT:    lvx 3, 0, 3
+; CHECK-NEXT:    vsubuwm 2, 3, 2
+; CHECK-NEXT:    blr
+  %e = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+  %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
+  ret <4 x i32> %r
+}
+
diff --git a/test/CodeGen/X86/signbit-shift.ll b/test/CodeGen/X86/signbit-shift.ll
index b22c1a34a3d..510bfe515ac 100644
--- a/test/CodeGen/X86/signbit-shift.ll
+++ b/test/CodeGen/X86/signbit-shift.ll
@@ -228,3 +228,28 @@ define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
+define i32 @sub_lshr(i32 %x) {
+; CHECK-LABEL: sub_lshr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shrl $31, %edi
+; CHECK-NEXT:    xorl $43, %edi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+  %sh = lshr i32 %x, 31
+  %r = sub i32 43, %sh
+  ret i32 %r
+}
+
+define <4 x i32> @sub_lshr_vec_splat(<4 x i32> %x) {
+; CHECK-LABEL: sub_lshr_vec_splat:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    psrld $31, %xmm0
+; CHECK-NEXT:    movdqa {{.*#+}} xmm1 = [42,42,42,42]
+; CHECK-NEXT:    psubd %xmm0, %xmm1
+; CHECK-NEXT:    movdqa %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %e = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+  %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
+  ret <4 x i32> %r
+}
+
-- 
2.50.1