From f64188b1bf64abcb6360025ec5cf1977b8ad4d10 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 20 Jul 2017 19:29:56 +0000 Subject: [PATCH] [X86] Add test case to demonstrate that we don't allow masks wider than 6 bits in the (shift x, (and y, mask)) patterns for the 64-bit memory form. We allow wider than 5 bits in the 16 and 32 bit store forms. And we allow wider than 6 bits on the 64-bit regsiter form.:w I'm assuming this was a mistake made back in r148024. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308656 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/shift-and.ll | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/test/CodeGen/X86/shift-and.ll b/test/CodeGen/X86/shift-and.ll index 75e2d233ed1..bb8eaa3c1cb 100644 --- a/test/CodeGen/X86/shift-and.ll +++ b/test/CodeGen/X86/shift-and.ll @@ -96,6 +96,21 @@ define i64 @t5(i64 %t, i64 %val) nounwind { ret i64 %res } +define void @t5ptr(i64 %t, i64* %ptr) nounwind { +; X64-LABEL: t5ptr: +; X64: ## BB#0: +; X64-NEXT: andb $-65, %dil +; X64-NEXT: movl %edi, %ecx +; X64-NEXT: shrq %cl, (%rsi) +; X64-NEXT: retq +; X64-NEXT: ## -- End function + %shamt = and i64 %t, 191 + %tmp = load i64, i64* %ptr + %tmp1 = lshr i64 %tmp, %shamt + store i64 %tmp1, i64* %ptr + ret void +} + ; rdar://11866926 define i64 @t6(i64 %key, i64* nocapture %val) nounwind { -- 2.50.1