From f46cbbae71a86cd7c2602bc45f171bfb224c4850 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 27 Mar 2019 15:41:00 +0000 Subject: [PATCH] AMDGPU: Fix areLoadsFromSameBasePtr for DS atomics The offset operand index is different for atomics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357073 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIInstrInfo.cpp | 15 +++++++++++---- .../AMDGPU/are-loads-from-same-base-ptr.ll | 17 +++++++++++++++++ 2 files changed, 28 insertions(+), 4 deletions(-) create mode 100644 test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp index 74e15dbb881..6155ad72f4c 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -167,12 +167,19 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, // Skip read2 / write2 variants for simplicity. // TODO: We should report true if the used offsets are adjacent (excluded // st64 versions). - if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 || - AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) + int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset); + int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); + if (Offset0Idx == -1 || Offset1Idx == -1) return false; - Offset0 = cast(Load0->getOperand(1))->getZExtValue(); - Offset1 = cast(Load1->getOperand(1))->getZExtValue(); + // XXX - be careful of datalesss loads + // getNamedOperandIdx returns the index for MachineInstrs. Since they + // include the output in the operand list, but SDNodes don't, we need to + // subtract the index by one. + Offset0Idx -= get(Opc0).NumDefs; + Offset1Idx -= get(Opc1).NumDefs; + Offset0 = cast(Load0->getOperand(Offset0Idx))->getZExtValue(); + Offset1 = cast(Load1->getOperand(Offset1Idx))->getZExtValue(); return true; } diff --git a/test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll b/test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll new file mode 100644 index 00000000000..6d26f571c72 --- /dev/null +++ b/test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; TII::areLoadsFromSameBasePtr failed because the offset for atomics +; is different from a normal load due to the data operand. + +; GCN-LABEL: {{^}}are_loads_from_same_base_ptr_ds_atomic: +; GCN: global_load_dword +; GCN: ds_min_u32 +; GCN: ds_max_u32 +define amdgpu_kernel void @are_loads_from_same_base_ptr_ds_atomic(i32 addrspace(1)* %arg0, i32 addrspace(3)* noalias %ptr0) #0 { + %tmp1 = load volatile i32, i32 addrspace(1)* %arg0 + %tmp2 = atomicrmw umin i32 addrspace(3)* %ptr0, i32 %tmp1 seq_cst + %tmp3 = atomicrmw umax i32 addrspace(3)* %ptr0, i32 %tmp1 seq_cst + ret void +} + +attributes #0 = { nounwind } -- 2.50.1