From f37518f80493a02bea64dd2776fadbe80b03d3f8 Mon Sep 17 00:00:00 2001
From: Amara Emerson <aemerson@apple.com>
Date: Sat, 21 Sep 2019 09:21:13 +0000
Subject: [PATCH] [AArch64][GlobalISel] Selection support for G_ASHR of <2 x
 s64>

Just add an extra case to the existing selection logic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372466 91177308-0d34-0410-b5e6-96231b3b80d8
---
 .../AArch64/AArch64InstructionSelector.cpp    |  6 +++-
 .../GlobalISel/select-vector-shift.mir        | 30 +++++++++++++++++++
 2 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 8503a0dbb06..223aa370e97 100644
--- a/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -1052,7 +1052,11 @@ bool AArch64InstructionSelector::selectVectorASHR(
   unsigned Opc = 0;
   unsigned NegOpc = 0;
   const TargetRegisterClass *RC = nullptr;
-  if (Ty == LLT::vector(4, 32)) {
+  if (Ty == LLT::vector(2, 64)) {
+    Opc = AArch64::SSHLv2i64;
+    NegOpc = AArch64::NEGv2i64;
+    RC = &AArch64::FPR128RegClass;
+  } else if (Ty == LLT::vector(4, 32)) {
     Opc = AArch64::SSHLv4i32;
     NegOpc = AArch64::NEGv4i32;
     RC = &AArch64::FPR128RegClass;
diff --git a/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir b/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
index 95da841e71d..b13c4b5ec0d 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
@@ -118,3 +118,33 @@ body:             |
     RET_ReallyLR implicit $q0
 
 ...
+---
+name:            ashr_v4i64
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+machineFunctionInfo: {}
+body:             |
+  bb.1:
+    liveins: $q0, $q1
+
+    ; CHECK-LABEL: name: ashr_v4i64
+    ; CHECK: liveins: $q0, $q1
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; CHECK: [[NEGv2i64_:%[0-9]+]]:fpr128 = NEGv2i64 [[COPY1]]
+    ; CHECK: [[SSHLv2i64_:%[0-9]+]]:fpr128 = SSHLv2i64 [[COPY]], [[NEGv2i64_]]
+    ; CHECK: $q0 = COPY [[SSHLv2i64_]]
+    ; CHECK: RET_ReallyLR implicit $q0
+    %0:fpr(<2 x s64>) = COPY $q0
+    %1:fpr(<2 x s64>) = COPY $q1
+    %2:fpr(<2 x s64>) = G_ASHR %0, %1(<2 x s64>)
+    $q0 = COPY %2(<2 x s64>)
+    RET_ReallyLR implicit $q0
+
+...
-- 
2.50.1