From f32cff39c140677f3f5be064896a4c33424a2f77 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 15 Nov 2016 00:05:42 +0000 Subject: [PATCH] AMDGPU: Set hasExtraSrcRegAllocReq on v_div_scale_* This doesn't solve any problems I know about, but this should have more conservative assumptions about the operands' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286913 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/VOP3Instructions.td | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/Target/AMDGPU/VOP3Instructions.td b/lib/Target/AMDGPU/VOP3Instructions.td index 87a7c4044ab..4f8b680e52f 100644 --- a/lib/Target/AMDGPU/VOP3Instructions.td +++ b/lib/Target/AMDGPU/VOP3Instructions.td @@ -167,11 +167,13 @@ def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile, AMDGPU def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> { let SchedRW = [WriteFloatFMA, WriteSALU]; + let hasExtraSrcRegAllocReq = 1; } // Double precision division pre-scale. def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> { let SchedRW = [WriteDouble, WriteSALU]; + let hasExtraSrcRegAllocReq = 1; } def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile, int_amdgcn_msad_u8>; -- 2.50.1