From f2fd62413a1714ec7e64204e39e9fe8ae77ee93f Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Tue, 10 May 2016 22:33:26 +0000
Subject: [PATCH] auto-generate checks

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269134 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/X86/rem.ll | 89 +++++++++++++++++++++++++++++++----------
 1 file changed, 68 insertions(+), 21 deletions(-)

diff --git a/test/CodeGen/X86/rem.ll b/test/CodeGen/X86/rem.ll
index 733b7942a6d..ffa24384c60 100644
--- a/test/CodeGen/X86/rem.ll
+++ b/test/CodeGen/X86/rem.ll
@@ -1,37 +1,84 @@
-; RUN: llc < %s -march=x86 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s
 
-; CHECK-LABEL: test1:
-; CHECK-NOT: div
 define i32 @test1(i32 %X) {
-        %tmp1 = srem i32 %X, 255                ; <i32> [#uses=1]
-        ret i32 %tmp1
+; CHECK-LABEL: test1:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movl $-2139062143, %edx # imm = 0xFFFFFFFF80808081
+; CHECK-NEXT:    movl %ecx, %eax
+; CHECK-NEXT:    imull %edx
+; CHECK-NEXT:    addl %ecx, %edx
+; CHECK-NEXT:    movl %edx, %eax
+; CHECK-NEXT:    shrl $31, %eax
+; CHECK-NEXT:    sarl $7, %edx
+; CHECK-NEXT:    addl %eax, %edx
+; CHECK-NEXT:    movl %edx, %eax
+; CHECK-NEXT:    shll $8, %eax
+; CHECK-NEXT:    subl %edx, %eax
+; CHECK-NEXT:    subl %eax, %ecx
+; CHECK-NEXT:    movl %ecx, %eax
+; CHECK-NEXT:    retl
+;
+  %tmp1 = srem i32 %X, 255
+  ret i32 %tmp1
 }
 
-; CHECK-LABEL: test2:
-; CHECK-NOT: div
 define i32 @test2(i32 %X) {
-        %tmp1 = srem i32 %X, 256                ; <i32> [#uses=1]
-        ret i32 %tmp1
+; CHECK-LABEL: test2:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    sarl $31, %ecx
+; CHECK-NEXT:    shrl $24, %ecx
+; CHECK-NEXT:    addl %eax, %ecx
+; CHECK-NEXT:    andl $-256, %ecx
+; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    retl
+;
+  %tmp1 = srem i32 %X, 256
+  ret i32 %tmp1
 }
 
-; CHECK-LABEL: test3:
-; CHECK-NOT: div
 define i32 @test3(i32 %X) {
-        %tmp1 = urem i32 %X, 255                ; <i32> [#uses=1]
-        ret i32 %tmp1
+; CHECK-LABEL: test3:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movl $-2139062143, %edx # imm = 0xFFFFFFFF80808081
+; CHECK-NEXT:    movl %ecx, %eax
+; CHECK-NEXT:    mull %edx
+; CHECK-NEXT:    shrl $7, %edx
+; CHECK-NEXT:    movl %edx, %eax
+; CHECK-NEXT:    shll $8, %eax
+; CHECK-NEXT:    subl %edx, %eax
+; CHECK-NEXT:    subl %eax, %ecx
+; CHECK-NEXT:    movl %ecx, %eax
+; CHECK-NEXT:    retl
+;
+  %tmp1 = urem i32 %X, 255
+  ret i32 %tmp1
 }
 
-; CHECK-LABEL: test4:
-; CHECK-NOT: div
 define i32 @test4(i32 %X) {
-        %tmp1 = urem i32 %X, 256                ; <i32> [#uses=1]
-        ret i32 %tmp1
+; CHECK-LABEL: test4:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    retl
+;
+  %tmp1 = urem i32 %X, 256
+  ret i32 %tmp1
 }
 
-; CHECK-LABEL: test5:
-; CHECK-NOT: cltd
 define i32 @test5(i32 %X) nounwind readnone {
+; CHECK-LABEL: test5:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    movl $41, %eax
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    idivl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl %edx, %eax
+; CHECK-NEXT:    retl
+;
 entry:
-	%0 = srem i32 41, %X
-	ret i32 %0
+  %0 = srem i32 41, %X
+  ret i32 %0
 }
-- 
2.50.1