From f25acacbe6e54a6a25d450767c021bc616adf939 Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Thu, 6 Apr 2017 22:42:18 +0000 Subject: [PATCH] Turn on -addr-sink-using-gep by default. The new codepath has been in the tree for years, and there isn't any reason to use two codepaths here. Differential Revision: https://reviews.llvm.org/D30596 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299723 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/CodeGenPrepare.cpp | 2 +- test/CodeGen/AArch64/aarch64-gep-opt.ll | 8 +++- .../AMDGPU/cgp-addressing-modes-flat.ll | 12 +++--- test/CodeGen/AMDGPU/cgp-addressing-modes.ll | 43 +++++++++---------- test/CodeGen/ARM/phi.ll | 1 - .../PowerPC/2007-11-16-landingpad-split.ll | 1 - test/CodeGen/PowerPC/ppc64-gep-opt.ll | 4 +- test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll | 1 - test/CodeGen/X86/MergeConsecutiveStores.ll | 1 - .../X86/codegen-prepare-addrmode-sext.ll | 41 ++++++------------ test/CodeGen/X86/codegen-prepare.ll | 1 - test/CodeGen/X86/isel-sink.ll | 1 - test/CodeGen/X86/merge_store.ll | 1 - .../CodeGenPrepare/X86/computedgoto.ll | 8 ++-- .../CodeGenPrepare/X86/sink-addrmode.ll | 26 +++++------ .../CodeGenPrepare/X86/sink-addrspacecast.ll | 5 +-- .../LoopStrengthReduce/ARM/ivchain-ARM.ll | 1 - .../LoopStrengthReduce/X86/ivchain-X86.ll | 2 - 18 files changed, 66 insertions(+), 93 deletions(-) diff --git a/lib/CodeGen/CodeGenPrepare.cpp b/lib/CodeGen/CodeGenPrepare.cpp index c53f827ebe6..e2bb3780e3e 100644 --- a/lib/CodeGen/CodeGenPrepare.cpp +++ b/lib/CodeGen/CodeGenPrepare.cpp @@ -96,7 +96,7 @@ static cl::opt DisableSelectToBranch( cl::desc("Disable select to branch conversion.")); static cl::opt AddrSinkUsingGEPs( - "addr-sink-using-gep", cl::Hidden, cl::init(false), + "addr-sink-using-gep", cl::Hidden, cl::init(true), cl::desc("Address sinking in CGP using GEPs.")); static cl::opt EnableAndCmpSinking( diff --git a/test/CodeGen/AArch64/aarch64-gep-opt.ll b/test/CodeGen/AArch64/aarch64-gep-opt.ll index 6e4a47b0440..df9534ffde0 100644 --- a/test/CodeGen/AArch64/aarch64-gep-opt.ll +++ b/test/CodeGen/AArch64/aarch64-gep-opt.ll @@ -96,9 +96,13 @@ exit: ; CHECK-NoAA: add i64 [[TMP:%[a-zA-Z0-9]+]], 528 ; CHECK-NoAA: add i64 [[TMP]], 532 ; CHECK-NoAA: if.true: -; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 532 +; CHECK-NoAA: inttoptr +; CHECK-NoAA: bitcast +; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, {{.*}}, i64 532 ; CHECK-NoAA: exit: -; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 528 +; CHECK-NoAA: inttoptr +; CHECK-NoAA: bitcast +; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, {{.*}}, i64 528 ; CHECK-UseAA-LABEL: test_GEP_across_BB( ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr diff --git a/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll b/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll index ac35dd0bef5..cbdcf6aeaf4 100644 --- a/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll +++ b/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll @@ -36,9 +36,9 @@ done: ; OPT-CI-NOT: getelementptr ; OPT: br i1 -; OPT-CI: ptrtoint -; OPT-CI: add -; OPT-CI: inttoptr +; OPT-CI: addrspacecast +; OPT-CI: getelementptr +; OPT-CI: bitcast ; OPT: br label ; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_global_i32: @@ -69,9 +69,9 @@ done: ; OPT-CI-NOT: getelementptr ; OPT: br i1 -; OPT-CI: ptrtoint -; OPT-CI: add -; OPT-CI: inttoptr +; OPT-CI: addrspacecast +; OPT-CI: getelementptr +; OPT-CI: bitcast ; OPT: br label ; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_constant_i32: diff --git a/test/CodeGen/AMDGPU/cgp-addressing-modes.ll b/test/CodeGen/AMDGPU/cgp-addressing-modes.ll index 46bd1940232..c1cf56e5058 100644 --- a/test/CodeGen/AMDGPU/cgp-addressing-modes.ll +++ b/test/CodeGen/AMDGPU/cgp-addressing-modes.ll @@ -11,7 +11,7 @@ target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24: ; OPT-CI-NOT: getelementptr i32, i32 addrspace(1)* %in ; OPT-VI: getelementptr i32, i32 addrspace(1)* %in ; OPT: br i1 -; OPT-CI: ptrtoint +; OPT-CI: getelementptr i8, ; GCN-LABEL: {{^}}test_sink_global_small_offset_i32: ; GCN: {{^}}BB0_2: @@ -124,7 +124,7 @@ done: ; OPT-LABEL: @test_sink_scratch_small_offset_i32( ; OPT-NOT: getelementptr [512 x i32] ; OPT: br i1 -; OPT: ptrtoint +; OPT: getelementptr i8, ; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32: ; GCN: s_and_saveexec_b64 @@ -162,7 +162,7 @@ done: ; OPT-LABEL: @test_sink_scratch_small_offset_i32_reserved( ; OPT-NOT: getelementptr [512 x i32] ; OPT: br i1 -; OPT: ptrtoint +; OPT: getelementptr i8, ; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32_reserved: ; GCN: s_and_saveexec_b64 @@ -488,7 +488,7 @@ done: %struct.foo = type { [3 x float], [3 x float] } ; OPT-LABEL: @sink_ds_address( -; OPT: ptrtoint %struct.foo addrspace(3)* %ptr to i32 +; OPT: getelementptr i8, ; GCN-LABEL: {{^}}sink_ds_address: ; GCN: s_load_dword [[SREG1:s[0-9]+]], @@ -519,8 +519,7 @@ bb34: ; OPT-LABEL: @test_sink_constant_small_max_mubuf_offset_load_i32_align_1( ; OPT: br i1 %tmp0, ; OPT: if: -; OPT: %sunkaddr = ptrtoint i8 addrspace(2)* %in to i64 -; OPT: %sunkaddr1 = add i64 %sunkaddr, 4095 +; OPT: getelementptr i8, {{.*}} 4095 define amdgpu_kernel void @test_sink_constant_small_max_mubuf_offset_load_i32_align_1(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 1024 @@ -544,10 +543,10 @@ done: } ; OPT-LABEL: @test_sink_local_small_offset_atomicrmw_i32( -; OPT: %sunkaddr = ptrtoint i32 addrspace(3)* %in to i32 -; OPT: %sunkaddr1 = add i32 %sunkaddr, 28 -; OPT: %sunkaddr2 = inttoptr i32 %sunkaddr1 to i32 addrspace(3)* -; OPT: %tmp1 = atomicrmw add i32 addrspace(3)* %sunkaddr2, i32 2 seq_cst +; OPT: %0 = bitcast i32 addrspace(3)* %in to i8 addrspace(3)* +; OPT: %sunkaddr = getelementptr i8, i8 addrspace(3)* %0, i32 28 +; OPT: %1 = bitcast i8 addrspace(3)* %sunkaddr to i32 addrspace(3)* +; OPT: %tmp1 = atomicrmw add i32 addrspace(3)* %1, i32 2 seq_cst define amdgpu_kernel void @test_sink_local_small_offset_atomicrmw_i32(i32 addrspace(3)* %out, i32 addrspace(3)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(3)* %out, i32 999999 @@ -570,10 +569,10 @@ done: } ; OPT-LABEL: @test_sink_local_small_offset_cmpxchg_i32( -; OPT: %sunkaddr = ptrtoint i32 addrspace(3)* %in to i32 -; OPT: %sunkaddr1 = add i32 %sunkaddr, 28 -; OPT: %sunkaddr2 = inttoptr i32 %sunkaddr1 to i32 addrspace(3)* -; OPT: %tmp1.struct = cmpxchg i32 addrspace(3)* %sunkaddr2, i32 undef, i32 2 seq_cst monotonic +; OPT: %0 = bitcast i32 addrspace(3)* %in to i8 addrspace(3)* +; OPT: %sunkaddr = getelementptr i8, i8 addrspace(3)* %0, i32 28 +; OPT: %1 = bitcast i8 addrspace(3)* %sunkaddr to i32 addrspace(3)* +; OPT: %tmp1.struct = cmpxchg i32 addrspace(3)* %1, i32 undef, i32 2 seq_cst monotonic define amdgpu_kernel void @test_sink_local_small_offset_cmpxchg_i32(i32 addrspace(3)* %out, i32 addrspace(3)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(3)* %out, i32 999999 @@ -623,10 +622,10 @@ done: } ; OPT-LABEL: @test_sink_local_small_offset_atomic_inc_i32( -; OPT: %sunkaddr = ptrtoint i32 addrspace(3)* %in to i32 -; OPT: %sunkaddr1 = add i32 %sunkaddr, 28 -; OPT: %sunkaddr2 = inttoptr i32 %sunkaddr1 to i32 addrspace(3)* -; OPT: %tmp1 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %sunkaddr2, i32 2, i32 0, i32 0, i1 false) +; OPT: %0 = bitcast i32 addrspace(3)* %in to i8 addrspace(3)* +; OPT: %sunkaddr = getelementptr i8, i8 addrspace(3)* %0, i32 28 +; OPT: %1 = bitcast i8 addrspace(3)* %sunkaddr to i32 addrspace(3)* +; OPT: %tmp1 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %1, i32 2, i32 0, i32 0, i1 false) define amdgpu_kernel void @test_sink_local_small_offset_atomic_inc_i32(i32 addrspace(3)* %out, i32 addrspace(3)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(3)* %out, i32 999999 @@ -649,10 +648,10 @@ done: } ; OPT-LABEL: @test_sink_local_small_offset_atomic_dec_i32( -; OPT: %sunkaddr = ptrtoint i32 addrspace(3)* %in to i32 -; OPT: %sunkaddr1 = add i32 %sunkaddr, 28 -; OPT: %sunkaddr2 = inttoptr i32 %sunkaddr1 to i32 addrspace(3)* -; OPT: %tmp1 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %sunkaddr2, i32 2, i32 0, i32 0, i1 false) +; OPT: %0 = bitcast i32 addrspace(3)* %in to i8 addrspace(3)* +; OPT: %sunkaddr = getelementptr i8, i8 addrspace(3)* %0, i32 28 +; OPT: %1 = bitcast i8 addrspace(3)* %sunkaddr to i32 addrspace(3)* +; OPT: %tmp1 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %1, i32 2, i32 0, i32 0, i1 false) define amdgpu_kernel void @test_sink_local_small_offset_atomic_dec_i32(i32 addrspace(3)* %out, i32 addrspace(3)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(3)* %out, i32 999999 diff --git a/test/CodeGen/ARM/phi.ll b/test/CodeGen/ARM/phi.ll index ff85052175c..568f7572b32 100644 --- a/test/CodeGen/ARM/phi.ll +++ b/test/CodeGen/ARM/phi.ll @@ -1,5 +1,4 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -; RUN: llc -mtriple=arm-eabi -mattr=+v4t -addr-sink-using-gep=1 %s -o - | FileCheck %s ; diff --git a/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll index bd496704890..53bad4fe06e 100644 --- a/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll +++ b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll @@ -1,5 +1,4 @@ ; RUN: llc -mcpu=g5 < %s | FileCheck %s -; RUN: llc -mcpu=g5 -addr-sink-using-gep=1 < %s | FileCheck %s ;; Formerly crashed, see PR 1508 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc64-apple-darwin8" diff --git a/test/CodeGen/PowerPC/ppc64-gep-opt.ll b/test/CodeGen/PowerPC/ppc64-gep-opt.ll index 1a78310ddf3..d1ae1bcbd88 100644 --- a/test/CodeGen/PowerPC/ppc64-gep-opt.ll +++ b/test/CodeGen/PowerPC/ppc64-gep-opt.ll @@ -84,9 +84,9 @@ exit: ; CHECK-NoAA: add i64 [[TMP:%[a-zA-Z0-9]+]], 528 ; CHECK-NoAA: add i64 [[TMP]], 532 ; CHECK-NoAA: if.true: -; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 532 +; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, i8* {{.*}}, i64 532 ; CHECK-NoAA: exit: -; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 528 +; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, i8* {{.*}}, i64 528 ; CHECK-UseAA-LABEL: test_GEP_across_BB( ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr diff --git a/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll b/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll index f159bcdee13..645221fe299 100644 --- a/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll +++ b/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=x86 -mtriple=i686-darwin | FileCheck %s -; RUN: llc < %s -march=x86 -mtriple=i686-darwin -addr-sink-using-gep=1 | FileCheck %s define void @foo(i8** %buf, i32 %size, i32 %col, i8* %p) nounwind { entry: diff --git a/test/CodeGen/X86/MergeConsecutiveStores.ll b/test/CodeGen/X86/MergeConsecutiveStores.ll index 29ecb7838a1..4303b625446 100644 --- a/test/CodeGen/X86/MergeConsecutiveStores.ll +++ b/test/CodeGen/X86/MergeConsecutiveStores.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -fixup-byte-word-insts=1 < %s | FileCheck -check-prefix=CHECK -check-prefix=BWON %s ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -fixup-byte-word-insts=0 < %s | FileCheck -check-prefix=CHECK -check-prefix=BWOFF %s -; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -addr-sink-using-gep=1 < %s | FileCheck -check-prefix=CHECK -check-prefix=BWON %s %struct.A = type { i8, i8, i8, i8, i8, i8, i8, i8 } %struct.B = type { i32, i32, i32, i32, i32, i32, i32, i32 } diff --git a/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll b/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll index f00c40ba3a9..1f4578c9531 100644 --- a/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll +++ b/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll @@ -1,5 +1,4 @@ ; RUN: opt -S -codegenprepare %s -o - | FileCheck %s -; RUN: opt -S -codegenprepare -addr-sink-using-gep=1 %s -o - | FileCheck -check-prefix=CHECK-GEP %s ; This file tests the different cases what are involved when codegen prepare ; tries to get sign/zero extension out of the way of addressing mode. ; This tests require an actual target as addressing mode decisions depends @@ -309,33 +308,18 @@ define i8 @twoArgsNoPromotionRemove(i1 %arg1, i8 %arg2, i8* %base) { ; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SHL]], %arg2 ; CHECK: [[SEXTADD:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64 ; BB then -; CHECK: [[BASE1:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTADD]], 48 -; CHECK: [[ADDR1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[BASE1]] to i32* +; CHECK: [[BASE1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to i32* +; CHECK: [[BCC1:%[a-zA-Z_0-9-]+]] = bitcast i32* [[BASE1]] to i8* +; CHECK: [[FULL1:%[a-zA-Z_0-9-]+]] = getelementptr i8, i8* [[BCC1]], i64 48 +; CHECK: [[ADDR1:%[a-zA-Z_0-9-]+]] = bitcast i8* [[FULL1]] to i32* ; CHECK: load i32, i32* [[ADDR1]] ; BB else -; CHECK: [[BASE2:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTADD]], 48 -; CHECK: [[ADDR2:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[BASE2]] to i32* +; CHECK: [[BASE2:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to i32* +; CHECK: [[BCC2:%[a-zA-Z_0-9-]+]] = bitcast i32* [[BASE2]] to i8* +; CHECK: [[FULL2:%[a-zA-Z_0-9-]+]] = getelementptr i8, i8* [[BCC2]], i64 48 +; CHECK: [[ADDR2:%[a-zA-Z_0-9-]+]] = bitcast i8* [[FULL2]] to i32* ; CHECK: load i32, i32* [[ADDR2]] ; CHECK: ret -; CHECK-GEP-LABEL: @checkProfitability -; CHECK-GEP-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg1 to i64 -; CHECK-GEP-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg2 to i64 -; CHECK-GEP: [[SHL:%[a-zA-Z_0-9-]+]] = shl nsw i32 %arg1, 1 -; CHECK-GEP: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SHL]], %arg2 -; CHECK-GEP: [[SEXTADD:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64 -; BB then -; CHECK-GEP: [[BASE1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to i32* -; CHECK-GEP: [[BCC1:%[a-zA-Z_0-9-]+]] = bitcast i32* [[BASE1]] to i8* -; CHECK-GEP: [[FULL1:%[a-zA-Z_0-9-]+]] = getelementptr i8, i8* [[BCC1]], i64 48 -; CHECK-GEP: [[ADDR1:%[a-zA-Z_0-9-]+]] = bitcast i8* [[FULL1]] to i32* -; CHECK-GEP: load i32, i32* [[ADDR1]] -; BB else -; CHECK-GEP: [[BASE2:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to i32* -; CHECK-GEP: [[BCC2:%[a-zA-Z_0-9-]+]] = bitcast i32* [[BASE2]] to i8* -; CHECK-GEP: [[FULL2:%[a-zA-Z_0-9-]+]] = getelementptr i8, i8* [[BCC2]], i64 48 -; CHECK-GEP: [[ADDR2:%[a-zA-Z_0-9-]+]] = bitcast i8* [[FULL2]] to i32* -; CHECK-GEP: load i32, i32* [[ADDR2]] -; CHECK-GEP: ret define i32 @checkProfitability(i32 %arg1, i32 %arg2, i1 %test) { %shl = shl nsw i32 %arg1, 1 %add1 = add nsw i32 %shl, %arg2 @@ -371,11 +355,10 @@ end: ; Use it at the starting point for the matching. ; CHECK: %conv.i = zext i16 [[PLAIN_OPND:%[.a-zA-Z_0-9-]+]] to i32 ; CHECK-NEXT: [[PROMOTED_CONV:%[.a-zA-Z_0-9-]+]] = zext i16 [[PLAIN_OPND]] to i64 -; CHECK-NEXT: [[BASE:%[a-zA-Z_0-9-]+]] = ptrtoint %struct.dns_packet* %P to i64 -; CHECK-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add i64 [[BASE]], [[PROMOTED_CONV]] -; CHECK-NEXT: [[ADDR:%[a-zA-Z_0-9-]+]] = add i64 [[ADD]], 7 -; CHECK-NEXT: [[CAST:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[ADDR]] to i8* -; CHECK-NEXT: load i8, i8* [[CAST]], align 1 +; CHECK-NEXT: [[BASE:%[a-zA-Z_0-9-]+]] = bitcast %struct.dns_packet* %P to i8* +; CHECK-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = getelementptr i8, i8* [[BASE]], i64 [[PROMOTED_CONV]] +; CHECK-NEXT: [[ADDR:%[a-zA-Z_0-9-]+]] = getelementptr i8, i8* [[ADD]], i64 7 +; CHECK-NEXT: load i8, i8* [[ADDR]], align 1 define signext i16 @fn3(%struct.dns_packet* nocapture readonly %P) { entry: %tmp = getelementptr inbounds %struct.dns_packet, %struct.dns_packet* %P, i64 0, i32 2 diff --git a/test/CodeGen/X86/codegen-prepare.ll b/test/CodeGen/X86/codegen-prepare.ll index e58bc22ef14..9d7d3d376cd 100644 --- a/test/CodeGen/X86/codegen-prepare.ll +++ b/test/CodeGen/X86/codegen-prepare.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s -; RUN: llc < %s -mtriple=x86_64-pc-linux -addr-sink-using-gep=1 | FileCheck %s ; Check that the CodeGenPrepare Pass ; does not wrongly rewrite the address computed by Instruction %4 diff --git a/test/CodeGen/X86/isel-sink.ll b/test/CodeGen/X86/isel-sink.ll index 27abe051a9b..2f32097a09b 100644 --- a/test/CodeGen/X86/isel-sink.ll +++ b/test/CodeGen/X86/isel-sink.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=x86 | FileCheck %s -; RUN: llc < %s -march=x86 -addr-sink-using-gep=1 | FileCheck %s define i32 @test(i32* %X, i32 %B) { ; CHECK-LABEL: test: diff --git a/test/CodeGen/X86/merge_store.ll b/test/CodeGen/X86/merge_store.ll index 2701f369bcd..31c1f658242 100644 --- a/test/CodeGen/X86/merge_store.ll +++ b/test/CodeGen/X86/merge_store.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -addr-sink-using-gep=1 | FileCheck %s define void @merge_store(i32* nocapture %a) { ; CHECK-LABEL: merge_store: diff --git a/test/Transforms/CodeGenPrepare/X86/computedgoto.ll b/test/Transforms/CodeGenPrepare/X86/computedgoto.ll index 7acaa455327..00a4df9b2c5 100644 --- a/test/Transforms/CodeGenPrepare/X86/computedgoto.ll +++ b/test/Transforms/CodeGenPrepare/X86/computedgoto.ll @@ -218,10 +218,10 @@ define void @nophi(i32* %p) { ; CHECK-NEXT: tail call void @use(i32 1) ; CHECK-NEXT: br label [[INDIRECTGOTO]] ; CHECK: indirectgoto: -; CHECK-NEXT: [[SUNKADDR:%.*]] = ptrtoint i32* [[P]] to i64 -; CHECK-NEXT: [[SUNKADDR1:%.*]] = add i64 [[SUNKADDR]], 4 -; CHECK-NEXT: [[SUNKADDR2:%.*]] = inttoptr i64 [[SUNKADDR1]] to i32* -; CHECK-NEXT: [[NEWP:%.*]] = load i32, i32* [[SUNKADDR2]], align 4 +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P]] to i8* +; CHECK-NEXT: [[SUNKADDR:%.*]] = getelementptr i8, i8* [[TMP0]], i64 4 +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[SUNKADDR]] to i32* +; CHECK-NEXT: [[NEWP:%.*]] = load i32, i32* [[TMP1]], align 4 ; CHECK-NEXT: [[IDX:%.*]] = sext i32 [[NEWP]] to i64 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* @nophi.targets, i64 0, i64 [[IDX]] ; CHECK-NEXT: [[NEWOP:%.*]] = load i8*, i8** [[ARRAYIDX]], align 8 diff --git a/test/Transforms/CodeGenPrepare/X86/sink-addrmode.ll b/test/Transforms/CodeGenPrepare/X86/sink-addrmode.ll index 5c0b5f3839d..9d6e668167f 100644 --- a/test/Transforms/CodeGenPrepare/X86/sink-addrmode.ll +++ b/test/Transforms/CodeGenPrepare/X86/sink-addrmode.ll @@ -7,7 +7,7 @@ target triple = "x86_64-unknown-linux-gnu" ; Can we sink single addressing mode computation to use? define void @test1(i1 %cond, i64* %base) { ; CHECK-LABEL: @test1 -; CHECK: add i64 {{.+}}, 40 +; CHECK: getelementptr i8, {{.+}} 40 entry: %addr = getelementptr inbounds i64, i64* %base, i64 5 %casted = bitcast i64* %addr to i32* @@ -33,7 +33,7 @@ entry: if.then: ; CHECK-LABEL: if.then: -; CHECK: add i64 {{.+}}, 40 +; CHECK: getelementptr i8, {{.+}} 40 %v1 = load i32, i32* %casted, align 4 call void @foo(i32 %v1) %cmp = icmp eq i32 %v1, 0 @@ -41,7 +41,7 @@ if.then: next: ; CHECK-LABEL: next: -; CHECK: add i64 {{.+}}, 40 +; CHECK: getelementptr i8, {{.+}} 40 %v2 = load i32, i32* %casted, align 4 call void @foo(i32 %v2) br label %fallthrough @@ -61,10 +61,10 @@ entry: if.then: ; CHECK-LABEL: if.then: -; CHECK: add i64 {{.+}}, 40 +; CHECK: getelementptr i8, {{.+}} 40 %v1 = load i32, i32* %casted, align 4 call void @foo(i32 %v1) -; CHECK-NOT: add i64 {{.+}}, 40 +; CHECK-NOT: getelementptr i8, {{.+}}, 40 %v2 = load i32, i32* %casted, align 4 call void @foo(i32 %v2) br label %fallthrough @@ -84,7 +84,7 @@ entry: if.then: ; CHECK-LABEL: if.then: -; CHECK: add i64 {{.+}}, 40 +; CHECK: getelementptr i8, {{.+}} 40 %v1 = load i32, i32* %casted, align 4 call void @foo(i32 %v1) %cmp = icmp eq i32 %v1, 0 @@ -95,7 +95,7 @@ fallthrough: rare.1: ; CHECK-LABEL: rare.1: -; CHECK: add i64 {{.+}}, 40 +; CHECK: getelementptr i8, {{.+}} 40 call void @slowpath(i32 %v1, i32* %casted) cold br label %fallthrough } @@ -111,7 +111,7 @@ entry: if.then: ; CHECK-LABEL: if.then: -; CHECK-NOT: add i64 {{.+}}, 40 +; CHECK-NOT: getelementptr i8, {{.+}} 40 %v1 = load i32, i32* %casted, align 4 call void @foo(i32 %v1) %cmp = icmp eq i32 %v1, 0 @@ -136,7 +136,7 @@ entry: if.then: ; CHECK-LABEL: if.then: -; CHECK-NOT: add i64 {{.+}}, 40 +; CHECK-NOT: getelementptr i8, {{.+}} 40 %v1 = load i32, i32* %casted, align 4 call void @foo(i32 %v1) %cmp = icmp eq i32 %v1, 0 @@ -162,7 +162,7 @@ entry: if.then: ; CHECK-LABEL: if.then: -; CHECK: add i64 {{.+}}, 40 +; CHECK: getelementptr i8, {{.+}} 40 %v1 = load i32, i32* %casted, align 4 call void @foo(i32 %v1) %cmp = icmp eq i32 %v1, 0 @@ -170,7 +170,7 @@ if.then: next: ; CHECK-LABEL: next: -; CHECK: add i64 {{.+}}, 40 +; CHECK: getelementptr i8, {{.+}} 40 %v2 = load i32, i32* %casted, align 4 call void @foo(i32 %v2) %cmp2 = icmp eq i32 %v2, 0 @@ -181,13 +181,13 @@ fallthrough: rare.1: ; CHECK-LABEL: rare.1: -; CHECK: add i64 {{.+}}, 40 +; CHECK: getelementptr i8, {{.+}} 40 call void @slowpath(i32 %v1, i32* %casted) cold br label %next rare.2: ; CHECK-LABEL: rare.2: -; CHECK: add i64 {{.+}}, 40 +; CHECK: getelementptr i8, {{.+}} 40 call void @slowpath(i32 %v2, i32* %casted) cold br label %fallthrough } diff --git a/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll b/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll index eb2c985c70e..31f0ca239e3 100644 --- a/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll +++ b/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll @@ -1,12 +1,10 @@ -; RUN: opt -S -codegenprepare < %s | FileCheck %s -check-prefix=CHECK -check-prefix=INT -; RUN: opt -S -codegenprepare -addr-sink-using-gep=true < %s | FileCheck %s -check-prefix=CHECK -check-prefix=GEP +; RUN: opt -S -codegenprepare < %s | FileCheck %s -check-prefix=CHECK -check-prefix=GEP target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" ; CHECK-LABEL: @load_cast_gep -; INT: add i64 %sunkaddr, 40 ; GEP: [[CAST:%[0-9]+]] = addrspacecast i64* %base to i8 addrspace(1)* ; GEP: getelementptr i8, i8 addrspace(1)* [[CAST]], i64 40 define void @load_cast_gep(i1 %cond, i64* %base) { @@ -24,7 +22,6 @@ fallthrough: } ; CHECK-LABEL: @store_gep_cast -; INT: add i64 %sunkaddr, 20 ; GEP: [[CAST:%[0-9]+]] = addrspacecast i64* %base to i8 addrspace(1)* ; GEP: getelementptr i8, i8 addrspace(1)* [[CAST]], i64 20 define void @store_gep_cast(i1 %cond, i64* %base) { diff --git a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll index 78884210108..a9d1e875876 100644 --- a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll +++ b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll @@ -1,5 +1,4 @@ ; RUN: llc -O3 -mtriple=thumb-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=A9 -; RUN: llc -O3 -mtriple=thumb-eabi -mcpu=cortex-a9 -addr-sink-using-gep=1 %s -o - | FileCheck %s -check-prefix=A9 ; @simple is the most basic chain of address induction variables. Chaining ; saves at least one register and avoids complex addressing and setup diff --git a/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll b/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll index ab7d4f1baa8..fb63b66137f 100644 --- a/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll +++ b/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll @@ -1,7 +1,5 @@ ; RUN: llc < %s -O3 -march=x86-64 -mcpu=core2 | FileCheck %s -check-prefix=X64 ; RUN: llc < %s -O3 -march=x86 -mcpu=core2 | FileCheck %s -check-prefix=X32 -; RUN: llc < %s -O3 -march=x86-64 -mcpu=core2 -addr-sink-using-gep=1 | FileCheck %s -check-prefix=X64 -; RUN: llc < %s -O3 -march=x86 -mcpu=core2 -addr-sink-using-gep=1 | FileCheck %s -check-prefix=X32 ; @simple is the most basic chain of address induction variables. Chaining ; saves at least one register and avoids complex addressing and setup -- 2.40.0