From f1e9f3e56b935ff0ff289f1d7d0e30402e1c8343 Mon Sep 17 00:00:00 2001 From: Cullen Rhodes Date: Fri, 31 May 2019 09:13:55 +0000 Subject: [PATCH] [AArch64][SVE2] Asm: support WHILE instructions Summary: Patch adds support for the following instructions: * WHILEGE, WHILEGT, WHILEHS, WHILEHI, WHILEWR, WHILERW The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62601 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362215 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64SVEInstrInfo.td | 15 +++++ lib/Target/AArch64/SVEInstrFormats.td | 26 +++++++++ test/MC/AArch64/SVE2/whilege-diagnostics.s | 29 +++++++++ test/MC/AArch64/SVE2/whilege.s | 68 ++++++++++++++++++++++ test/MC/AArch64/SVE2/whilegt-diagnostics.s | 29 +++++++++ test/MC/AArch64/SVE2/whilegt.s | 68 ++++++++++++++++++++++ test/MC/AArch64/SVE2/whilehi-diagnostics.s | 29 +++++++++ test/MC/AArch64/SVE2/whilehi.s | 68 ++++++++++++++++++++++ test/MC/AArch64/SVE2/whilehs-diagnostics.s | 29 +++++++++ test/MC/AArch64/SVE2/whilehs.s | 68 ++++++++++++++++++++++ test/MC/AArch64/SVE2/whilerw-diagnostics.s | 25 ++++++++ test/MC/AArch64/SVE2/whilerw.s | 32 ++++++++++ test/MC/AArch64/SVE2/whilewr-diagnostics.s | 25 ++++++++ test/MC/AArch64/SVE2/whilewr.s | 32 ++++++++++ 14 files changed, 543 insertions(+) create mode 100644 test/MC/AArch64/SVE2/whilege-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/whilege.s create mode 100644 test/MC/AArch64/SVE2/whilegt-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/whilegt.s create mode 100644 test/MC/AArch64/SVE2/whilehi-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/whilehi.s create mode 100644 test/MC/AArch64/SVE2/whilehs-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/whilehs.s create mode 100644 test/MC/AArch64/SVE2/whilerw-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/whilerw.s create mode 100644 test/MC/AArch64/SVE2/whilewr-diagnostics.s create mode 100644 test/MC/AArch64/SVE2/whilewr.s diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td index 6a6fedd0303..79ab42f4c08 100644 --- a/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1371,6 +1371,21 @@ let Predicates = [HasSVE2] in { // SVE table lookup (three sources) defm TBL_ZZZZ : sve2_int_perm_tbl<"tbl">; defm TBX_ZZZ : sve2_int_perm_tbx<"tbx">; + + // SVE integer compare scalar count and limit + defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege">; + defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt">; + defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs">; + defm WHILEHI_PWW : sve_int_while4_rr<0b101, "whilehi">; + + defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege">; + defm WHILEGT_PXX : sve_int_while8_rr<0b001, "whilegt">; + defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs">; + defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi">; + + // SVE pointer conflict compare + defm WHILEWR_PXX : sve2_int_while_rr<0b0, "whilewr">; + defm WHILERW_PXX : sve2_int_while_rr<0b1, "whilerw">; } let Predicates = [HasSVE2AES] in { diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td index c06b23eca1b..808e5946708 100644 --- a/lib/Target/AArch64/SVEInstrFormats.td +++ b/lib/Target/AArch64/SVEInstrFormats.td @@ -3270,6 +3270,32 @@ multiclass sve_int_while8_rr opc, string asm> { def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64>; } +class sve2_int_while_rr sz8_64, bits<1> rw, string asm, + PPRRegOp pprty> +: I<(outs pprty:$Pd), (ins GPR64:$Rn, GPR64:$Rm), + asm, "\t$Pd, $Rn, $Rm", + "", []>, Sched<[]> { + bits<4> Pd; + bits<5> Rm; + bits<5> Rn; + let Inst{31-24} = 0b00100101; + let Inst{23-22} = sz8_64; + let Inst{21} = 0b1; + let Inst{20-16} = Rm; + let Inst{15-10} = 0b001100; + let Inst{9-5} = Rn; + let Inst{4} = rw; + let Inst{3-0} = Pd; + + let Defs = [NZCV]; +} + +multiclass sve2_int_while_rr rw, string asm> { + def _B : sve2_int_while_rr<0b00, rw, asm, PPR8>; + def _H : sve2_int_while_rr<0b01, rw, asm, PPR16>; + def _S : sve2_int_while_rr<0b10, rw, asm, PPR32>; + def _D : sve2_int_while_rr<0b11, rw, asm, PPR64>; +} //===----------------------------------------------------------------------===// // SVE Floating Point Fast Reduction Group diff --git a/test/MC/AArch64/SVE2/whilege-diagnostics.s b/test/MC/AArch64/SVE2/whilege-diagnostics.s new file mode 100644 index 00000000000..974deb0597b --- /dev/null +++ b/test/MC/AArch64/SVE2/whilege-diagnostics.s @@ -0,0 +1,29 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilege p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilege p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilege p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilege p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilege p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilege p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +whilege p15, w0, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: whilege p15, w0, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/whilege.s b/test/MC/AArch64/SVE2/whilege.s new file mode 100644 index 00000000000..a506794f449 --- /dev/null +++ b/test/MC/AArch64/SVE2/whilege.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilege p15.b, xzr, x0 +// CHECK-INST: whilege p15.b, xzr, x0 +// CHECK-ENCODING: [0xef,0x13,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ef 13 20 25 + +whilege p15.b, x0, xzr +// CHECK-INST: whilege p15.b, x0, xzr +// CHECK-ENCODING: [0x0f,0x10,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 10 3f 25 + +whilege p15.b, wzr, w0 +// CHECK-INST: whilege p15.b, wzr, w0 +// CHECK-ENCODING: [0xef,0x03,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ef 03 20 25 + +whilege p15.b, w0, wzr +// CHECK-INST: whilege p15.b, w0, wzr +// CHECK-ENCODING: [0x0f,0x00,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 00 3f 25 + +whilege p15.h, x0, xzr +// CHECK-INST: whilege p15.h, x0, xzr +// CHECK-ENCODING: [0x0f,0x10,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 10 7f 25 + +whilege p15.h, w0, wzr +// CHECK-INST: whilege p15.h, w0, wzr +// CHECK-ENCODING: [0x0f,0x00,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 00 7f 25 + +whilege p15.s, x0, xzr +// CHECK-INST: whilege p15.s, x0, xzr +// CHECK-ENCODING: [0x0f,0x10,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 10 bf 25 + +whilege p15.s, w0, wzr +// CHECK-INST: whilege p15.s, w0, wzr +// CHECK-ENCODING: [0x0f,0x00,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 00 bf 25 + +whilege p15.d, w0, wzr +// CHECK-INST: whilege p15.d, w0, wzr +// CHECK-ENCODING: [0x0f,0x00,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 00 ff 25 + +whilege p15.d, x0, xzr +// CHECK-INST: whilege p15.d, x0, xzr +// CHECK-ENCODING: [0x0f,0x10,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 10 ff 25 diff --git a/test/MC/AArch64/SVE2/whilegt-diagnostics.s b/test/MC/AArch64/SVE2/whilegt-diagnostics.s new file mode 100644 index 00000000000..4d8e35146a5 --- /dev/null +++ b/test/MC/AArch64/SVE2/whilegt-diagnostics.s @@ -0,0 +1,29 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilegt p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilegt p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilegt p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilegt p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilegt p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilegt p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +whilegt p15, w0, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: whilegt p15, w0, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/whilegt.s b/test/MC/AArch64/SVE2/whilegt.s new file mode 100644 index 00000000000..3f307bcc56a --- /dev/null +++ b/test/MC/AArch64/SVE2/whilegt.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilegt p15.b, xzr, x0 +// CHECK-INST: whilegt p15.b, xzr, x0 +// CHECK-ENCODING: [0xff,0x13,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 13 20 25 + +whilegt p15.b, x0, xzr +// CHECK-INST: whilegt p15.b, x0, xzr +// CHECK-ENCODING: [0x1f,0x10,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 10 3f 25 + +whilegt p15.b, wzr, w0 +// CHECK-INST: whilegt p15.b, wzr, w0 +// CHECK-ENCODING: [0xff,0x03,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 03 20 25 + +whilegt p15.b, w0, wzr +// CHECK-INST: whilegt p15.b, w0, wzr +// CHECK-ENCODING: [0x1f,0x00,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 00 3f 25 + +whilegt p15.h, x0, xzr +// CHECK-INST: whilegt p15.h, x0, xzr +// CHECK-ENCODING: [0x1f,0x10,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 10 7f 25 + +whilegt p15.h, w0, wzr +// CHECK-INST: whilegt p15.h, w0, wzr +// CHECK-ENCODING: [0x1f,0x00,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 00 7f 25 + +whilegt p15.s, x0, xzr +// CHECK-INST: whilegt p15.s, x0, xzr +// CHECK-ENCODING: [0x1f,0x10,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 10 bf 25 + +whilegt p15.s, w0, wzr +// CHECK-INST: whilegt p15.s, w0, wzr +// CHECK-ENCODING: [0x1f,0x00,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 00 bf 25 + +whilegt p15.d, w0, wzr +// CHECK-INST: whilegt p15.d, w0, wzr +// CHECK-ENCODING: [0x1f,0x00,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 00 ff 25 + +whilegt p15.d, x0, xzr +// CHECK-INST: whilegt p15.d, x0, xzr +// CHECK-ENCODING: [0x1f,0x10,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 10 ff 25 diff --git a/test/MC/AArch64/SVE2/whilehi-diagnostics.s b/test/MC/AArch64/SVE2/whilehi-diagnostics.s new file mode 100644 index 00000000000..d5c278409f8 --- /dev/null +++ b/test/MC/AArch64/SVE2/whilehi-diagnostics.s @@ -0,0 +1,29 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilehi p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilehi p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilehi p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilehi p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilehi p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilehi p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +whilehi p15, w0, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: whilehi p15, w0, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/whilehi.s b/test/MC/AArch64/SVE2/whilehi.s new file mode 100644 index 00000000000..8e6272dd023 --- /dev/null +++ b/test/MC/AArch64/SVE2/whilehi.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilehi p15.b, xzr, x0 +// CHECK-INST: whilehi p15.b, xzr, x0 +// CHECK-ENCODING: [0xff,0x1b,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 1b 20 25 + +whilehi p15.b, x0, xzr +// CHECK-INST: whilehi p15.b, x0, xzr +// CHECK-ENCODING: [0x1f,0x18,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 18 3f 25 + +whilehi p15.b, wzr, w0 +// CHECK-INST: whilehi p15.b, wzr, w0 +// CHECK-ENCODING: [0xff,0x0b,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 0b 20 25 + +whilehi p15.b, w0, wzr +// CHECK-INST: whilehi p15.b, w0, wzr +// CHECK-ENCODING: [0x1f,0x08,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 08 3f 25 + +whilehi p15.h, x0, xzr +// CHECK-INST: whilehi p15.h, x0, xzr +// CHECK-ENCODING: [0x1f,0x18,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 18 7f 25 + +whilehi p15.h, w0, wzr +// CHECK-INST: whilehi p15.h, w0, wzr +// CHECK-ENCODING: [0x1f,0x08,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 08 7f 25 + +whilehi p15.s, x0, xzr +// CHECK-INST: whilehi p15.s, x0, xzr +// CHECK-ENCODING: [0x1f,0x18,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 18 bf 25 + +whilehi p15.s, w0, wzr +// CHECK-INST: whilehi p15.s, w0, wzr +// CHECK-ENCODING: [0x1f,0x08,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 08 bf 25 + +whilehi p15.d, w0, wzr +// CHECK-INST: whilehi p15.d, w0, wzr +// CHECK-ENCODING: [0x1f,0x08,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 08 ff 25 + +whilehi p15.d, x0, xzr +// CHECK-INST: whilehi p15.d, x0, xzr +// CHECK-ENCODING: [0x1f,0x18,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 18 ff 25 diff --git a/test/MC/AArch64/SVE2/whilehs-diagnostics.s b/test/MC/AArch64/SVE2/whilehs-diagnostics.s new file mode 100644 index 00000000000..b1ddafeedca --- /dev/null +++ b/test/MC/AArch64/SVE2/whilehs-diagnostics.s @@ -0,0 +1,29 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilehs p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilehs p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilehs p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilehs p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilehs p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilehs p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +whilehs p15, w0, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: whilehs p15, w0, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/whilehs.s b/test/MC/AArch64/SVE2/whilehs.s new file mode 100644 index 00000000000..1e01a1964be --- /dev/null +++ b/test/MC/AArch64/SVE2/whilehs.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilehs p15.b, xzr, x0 +// CHECK-INST: whilehs p15.b, xzr, x0 +// CHECK-ENCODING: [0xef,0x1b,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ef 1b 20 25 + +whilehs p15.b, x0, xzr +// CHECK-INST: whilehs p15.b, x0, xzr +// CHECK-ENCODING: [0x0f,0x18,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 18 3f 25 + +whilehs p15.b, wzr, w0 +// CHECK-INST: whilehs p15.b, wzr, w0 +// CHECK-ENCODING: [0xef,0x0b,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ef 0b 20 25 + +whilehs p15.b, w0, wzr +// CHECK-INST: whilehs p15.b, w0, wzr +// CHECK-ENCODING: [0x0f,0x08,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 08 3f 25 + +whilehs p15.h, x0, xzr +// CHECK-INST: whilehs p15.h, x0, xzr +// CHECK-ENCODING: [0x0f,0x18,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 18 7f 25 + +whilehs p15.h, w0, wzr +// CHECK-INST: whilehs p15.h, w0, wzr +// CHECK-ENCODING: [0x0f,0x08,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 08 7f 25 + +whilehs p15.s, x0, xzr +// CHECK-INST: whilehs p15.s, x0, xzr +// CHECK-ENCODING: [0x0f,0x18,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 18 bf 25 + +whilehs p15.s, w0, wzr +// CHECK-INST: whilehs p15.s, w0, wzr +// CHECK-ENCODING: [0x0f,0x08,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 08 bf 25 + +whilehs p15.d, w0, wzr +// CHECK-INST: whilehs p15.d, w0, wzr +// CHECK-ENCODING: [0x0f,0x08,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 08 ff 25 + +whilehs p15.d, x0, xzr +// CHECK-INST: whilehs p15.d, x0, xzr +// CHECK-ENCODING: [0x0f,0x18,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 18 ff 25 diff --git a/test/MC/AArch64/SVE2/whilerw-diagnostics.s b/test/MC/AArch64/SVE2/whilerw-diagnostics.s new file mode 100644 index 00000000000..5ea3b6d3a2e --- /dev/null +++ b/test/MC/AArch64/SVE2/whilerw-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilerw p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilerw p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilerw p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilerw p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilerw p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilerw p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilerw p15.b, w0, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilerw p15.b, w0, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/whilerw.s b/test/MC/AArch64/SVE2/whilerw.s new file mode 100644 index 00000000000..b4a5bd0962f --- /dev/null +++ b/test/MC/AArch64/SVE2/whilerw.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilerw p15.b, x30, x30 +// CHECK-INST: whilerw p15.b, x30, x30 +// CHECK-ENCODING: [0xdf,0x33,0x3e,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 33 3e 25 + +whilerw p15.h, x30, x30 +// CHECK-INST: whilerw p15.h, x30, x30 +// CHECK-ENCODING: [0xdf,0x33,0x7e,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 33 7e 25 + +whilerw p15.s, x30, x30 +// CHECK-INST: whilerw p15.s, x30, x30 +// CHECK-ENCODING: [0xdf,0x33,0xbe,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 33 be 25 + +whilerw p15.d, x30, x30 +// CHECK-INST: whilerw p15.d, x30, x30 +// CHECK-ENCODING: [0xdf,0x33,0xfe,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 33 fe 25 diff --git a/test/MC/AArch64/SVE2/whilewr-diagnostics.s b/test/MC/AArch64/SVE2/whilewr-diagnostics.s new file mode 100644 index 00000000000..b2e202985d9 --- /dev/null +++ b/test/MC/AArch64/SVE2/whilewr-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilewr p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilewr p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilewr p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilewr p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilewr p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilewr p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilewr p15.b, w0, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilewr p15.b, w0, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/whilewr.s b/test/MC/AArch64/SVE2/whilewr.s new file mode 100644 index 00000000000..588d1b2262b --- /dev/null +++ b/test/MC/AArch64/SVE2/whilewr.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilewr p15.b, x30, x30 +// CHECK-INST: whilewr p15.b, x30, x30 +// CHECK-ENCODING: [0xcf,0x33,0x3e,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: cf 33 3e 25 + +whilewr p15.h, x30, x30 +// CHECK-INST: whilewr p15.h, x30, x30 +// CHECK-ENCODING: [0xcf,0x33,0x7e,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: cf 33 7e 25 + +whilewr p15.s, x30, x30 +// CHECK-INST: whilewr p15.s, x30, x30 +// CHECK-ENCODING: [0xcf,0x33,0xbe,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: cf 33 be 25 + +whilewr p15.d, x30, x30 +// CHECK-INST: whilewr p15.d, x30, x30 +// CHECK-ENCODING: [0xcf,0x33,0xfe,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: cf 33 fe 25 -- 2.40.0