From f1ceb93f0d5be5f1e7420d816540d75effcfc0c7 Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Fri, 10 Jun 2016 20:50:33 +0000 Subject: [PATCH] [IRTranslator] Rework the comments for the methods to translate. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272432 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../llvm/CodeGen/GlobalISel/IRTranslator.h | 68 ++++++++++--------- 1 file changed, 35 insertions(+), 33 deletions(-) diff --git a/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/include/llvm/CodeGen/GlobalISel/IRTranslator.h index 5e38b6195c3..833e87493ca 100644 --- a/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -66,41 +66,48 @@ private: DenseMap BBToMBB; - /* A bunch of methods targeting ADD, SUB, etc. */ - // Return true if the translation was successful, false - // otherwise. - // Note: The MachineIRBuilder would encapsulate a - // MachineRegisterInfo to create virtual registers. - // - // Algo: - // 1. Look for a virtual register for each operand or - // create one. - // 2 Update the ValToVReg accordingly. - // 2.alt. For constant arguments, if they are compile time constants, - // produce an immediate in the right operand and do not touch - // ValToReg. Actually we will go with a virtual register for each - // constants because it may be expensive to actually materialize the - // constant. Moreover, if the constant spans on several instructions, - // CSE may not catch them. - // => Update ValToVReg and remember that we saw a constant in Constants. - // We will materialize all the constants in finalize. - // Note: we would need to do something so that we can recognize such operand - // as constants. - // 3. Create the generic instruction. - - bool translateBr(const Instruction &Inst); - - bool translateReturn(const Instruction &Inst); + /// Methods for translating form LLVM IR to MachineInstr. + /// \see ::translate for general information on the translate methods. + /// @{ - /// Translate \p Inst into a binary operation \p Opcode. - /// Insert the newly translated instruction right where the MIRBuilder + /// Translate \p Inst into its corresponding MachineInstr instruction(s). + /// Insert the newly translated instruction(s) right where the MIRBuilder /// is set. /// - /// \pre \p Inst is a binary operation. + /// The general algorithm is: + /// 1. Look for a virtual register for each operand or + /// create one. + /// 2 Update the ValToVReg accordingly. + /// 2.alt. For constant arguments, if they are compile time constants, + /// produce an immediate in the right operand and do not touch + /// ValToReg. Actually we will go with a virtual register for each + /// constants because it may be expensive to actually materialize the + /// constant. Moreover, if the constant spans on several instructions, + /// CSE may not catch them. + /// => Update ValToVReg and remember that we saw a constant in Constants. + /// We will materialize all the constants in finalize. + /// Note: we would need to do something so that we can recognize such operand + /// as constants. + /// 3. Create the generic instruction. /// /// \return true if the translation succeeded. + bool translate(const Instruction &Inst); + + /// Translate \p Inst into a binary operation \p Opcode. + /// \pre \p Inst is a binary operation. bool translateBinaryOp(unsigned Opcode, const Instruction &Inst); + /// Translate branch (br) instruction. + /// \pre \p Inst is a branch instruction. + bool translateBr(const Instruction &Inst); + + /// Translate return (ret) instruction. + /// The target needs to implement CallLowering::lowerReturn for + /// this to succeed. + /// \pre \p Inst is a return instruction. + bool translateReturn(const Instruction &Inst); + /// @} + // Builder for machine instruction a la IRBuilder. // I.e., compared to regular MIBuilder, this one also inserts the instruction // in the current block, it can creates block, etc., basically a kind of @@ -110,11 +117,6 @@ private: /// MachineRegisterInfo used to create virtual registers. MachineRegisterInfo *MRI; - // Return true if the translation from LLVM IR to Machine IR - // suceeded. - // See translateXXX for details. - bool translate(const Instruction &); - // * Insert all the code needed to materialize the constants // at the proper place. E.g., Entry block or dominator block // of each constant depending on how fancy we want to be. -- 2.50.1