From f167493b19f9d629128ba914236ef7cb82934e56 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Thu, 6 Apr 2017 09:49:34 +0000 Subject: [PATCH] [globalisel][tablegen] Move InstructionSelector declarations to anonymous namespaces Summary: This resolves the issue of tablegen-erated includes in the headers for non-GlobalISel builds in a simpler way than before. Reviewers: qcolombet, ab Reviewed By: ab Subscribers: igorb, ab, mgorny, dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30998 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299637 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64.h | 6 ++ .../AArch64/AArch64InstructionSelector.cpp | 53 ++++++++++++- .../AArch64/AArch64InstructionSelector.h | 74 ------------------- lib/Target/AArch64/AArch64TargetMachine.cpp | 4 +- lib/Target/AArch64/AArch64TargetMachine.h | 2 + lib/Target/X86/X86.h | 6 ++ lib/Target/X86/X86InstructionSelector.cpp | 50 ++++++++++++- lib/Target/X86/X86InstructionSelector.h | 72 ------------------ lib/Target/X86/X86TargetMachine.cpp | 4 +- lib/Target/X86/X86TargetMachine.h | 2 + 10 files changed, 120 insertions(+), 153 deletions(-) delete mode 100644 lib/Target/AArch64/AArch64InstructionSelector.h delete mode 100644 lib/Target/X86/X86InstructionSelector.h diff --git a/lib/Target/AArch64/AArch64.h b/lib/Target/AArch64/AArch64.h index fd106a8d9b0..b44b13e36e1 100644 --- a/lib/Target/AArch64/AArch64.h +++ b/lib/Target/AArch64/AArch64.h @@ -22,8 +22,11 @@ namespace llvm { +class AArch64RegisterBankInfo; +class AArch64Subtarget; class AArch64TargetMachine; class FunctionPass; +class InstructionSelector; class MachineFunctionPass; FunctionPass *createAArch64DeadRegisterDefinitions(); @@ -45,6 +48,9 @@ FunctionPass *createAArch64A53Fix835769(); FunctionPass *createAArch64CleanupLocalDynamicTLSPass(); FunctionPass *createAArch64CollectLOHPass(); +InstructionSelector * +createAArch64InstructionSelector(const AArch64TargetMachine &, + AArch64Subtarget &, AArch64RegisterBankInfo &); void initializeAArch64A53Fix835769Pass(PassRegistry&); void initializeAArch64A57FPLoadBalancingPass(PassRegistry&); diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp index 875e8b175b9..878dac6bff1 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -12,7 +12,6 @@ /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// -#include "AArch64InstructionSelector.h" #include "AArch64InstrInfo.h" #include "AArch64MachineFunctionInfo.h" #include "AArch64RegisterBankInfo.h" @@ -20,10 +19,12 @@ #include "AArch64Subtarget.h" #include "AArch64TargetMachine.h" #include "MCTargetDesc/AArch64AddressingModes.h" +#include "llvm/CodeGen/GlobalISel/InstructionSelector.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/IR/Type.h" #include "llvm/Support/Debug.h" @@ -37,6 +38,47 @@ using namespace llvm; #error "You shouldn't build this" #endif +namespace { + +class AArch64InstructionSelector : public InstructionSelector { +public: + AArch64InstructionSelector(const AArch64TargetMachine &TM, + const AArch64Subtarget &STI, + const AArch64RegisterBankInfo &RBI); + + bool select(MachineInstr &I) const override; + +private: + /// tblgen-erated 'select' implementation, used as the initial selector for + /// the patterns that don't require complex C++. + bool selectImpl(MachineInstr &I) const; + + bool selectVaStartAAPCS(MachineInstr &I, MachineFunction &MF, + MachineRegisterInfo &MRI) const; + bool selectVaStartDarwin(MachineInstr &I, MachineFunction &MF, + MachineRegisterInfo &MRI) const; + + bool selectCompareBranch(MachineInstr &I, MachineFunction &MF, + MachineRegisterInfo &MRI) const; + + bool selectArithImmed(MachineOperand &Root, MachineOperand &Result1, + MachineOperand &Result2) const; + + const AArch64TargetMachine &TM; + const AArch64Subtarget &STI; + const AArch64InstrInfo &TII; + const AArch64RegisterInfo &TRI; + const AArch64RegisterBankInfo &RBI; + +// We declare the temporaries used by selectImpl() in the class to minimize the +// cost of constructing placeholder values. +#define GET_GLOBALISEL_TEMPORARIES_DECL +#include "AArch64GenGlobalISel.inc" +#undef GET_GLOBALISEL_TEMPORARIES_DECL +}; + +} // end anonymous namespace + #define GET_GLOBALISEL_IMPL #include "AArch64GenGlobalISel.inc" #undef GET_GLOBALISEL_IMPL @@ -1315,3 +1357,12 @@ bool AArch64InstructionSelector::selectArithImmed( Result2.clearParent(); return true; } + +namespace llvm { +InstructionSelector * +createAArch64InstructionSelector(const AArch64TargetMachine &TM, + AArch64Subtarget &Subtarget, + AArch64RegisterBankInfo &RBI) { + return new AArch64InstructionSelector(TM, Subtarget, RBI); +} +} diff --git a/lib/Target/AArch64/AArch64InstructionSelector.h b/lib/Target/AArch64/AArch64InstructionSelector.h deleted file mode 100644 index c5476c4fbb7..00000000000 --- a/lib/Target/AArch64/AArch64InstructionSelector.h +++ /dev/null @@ -1,74 +0,0 @@ -//===- AArch64InstructionSelector --------------------------------*- C++ -*-==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -/// \file -/// This file declares the targeting of the InstructionSelector class for -/// AArch64. -//===----------------------------------------------------------------------===// - -#ifdef LLVM_BUILD_GLOBAL_ISEL - -#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRUCTIONSELECTOR_H -#define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRUCTIONSELECTOR_H - -#include "llvm/CodeGen/GlobalISel/InstructionSelector.h" -#include "llvm/CodeGen/MachineOperand.h" - -namespace llvm { - -class AArch64InstrInfo; -class AArch64RegisterBankInfo; -class AArch64RegisterInfo; -class AArch64Subtarget; -class AArch64TargetMachine; -class MachineOperand; - -class MachineFunction; -class MachineRegisterInfo; - -class AArch64InstructionSelector : public InstructionSelector { -public: - AArch64InstructionSelector(const AArch64TargetMachine &TM, - const AArch64Subtarget &STI, - const AArch64RegisterBankInfo &RBI); - - bool select(MachineInstr &I) const override; - -private: - /// tblgen-erated 'select' implementation, used as the initial selector for - /// the patterns that don't require complex C++. - bool selectImpl(MachineInstr &I) const; - - bool selectVaStartAAPCS(MachineInstr &I, MachineFunction &MF, - MachineRegisterInfo &MRI) const; - bool selectVaStartDarwin(MachineInstr &I, MachineFunction &MF, - MachineRegisterInfo &MRI) const; - - bool selectCompareBranch(MachineInstr &I, MachineFunction &MF, - MachineRegisterInfo &MRI) const; - - bool selectArithImmed(MachineOperand &Root, MachineOperand &Result1, - MachineOperand &Result2) const; - - const AArch64TargetMachine &TM; - const AArch64Subtarget &STI; - const AArch64InstrInfo &TII; - const AArch64RegisterInfo &TRI; - const AArch64RegisterBankInfo &RBI; - -// We declare the temporaries used by selectImpl() in the class to minimize the -// cost of constructing placeholder values. -#define GET_GLOBALISEL_TEMPORARIES_DECL -#include "AArch64GenGlobalISel.inc" -#undef GET_GLOBALISEL_TEMPORARIES_DECL -}; - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_AARCH64_AARCH64INSTRUCTIONSELECTOR_H -#endif // LLVM_BUILD_GLOBAL_ISEL diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp index e32777f57da..dcc51bf0232 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -12,7 +12,6 @@ #include "AArch64.h" #include "AArch64CallLowering.h" -#include "AArch64InstructionSelector.h" #include "AArch64LegalizerInfo.h" #include "AArch64MacroFusion.h" #ifdef LLVM_BUILD_GLOBAL_ISEL @@ -286,7 +285,8 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const { // FIXME: At this point, we can't rely on Subtarget having RBI. // It's awkward to mix passing RBI and the Subtarget; should we pass // TII/TRI as well? - GISel->InstSelector.reset(new AArch64InstructionSelector(*this, *I, *RBI)); + GISel->InstSelector.reset( + createAArch64InstructionSelector(*this, *I, *RBI)); GISel->RegBankInfo.reset(RBI); #endif diff --git a/lib/Target/AArch64/AArch64TargetMachine.h b/lib/Target/AArch64/AArch64TargetMachine.h index 6fa5e83957e..2c75a3258c1 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.h +++ b/lib/Target/AArch64/AArch64TargetMachine.h @@ -21,6 +21,8 @@ namespace llvm { +class AArch64RegisterBankInfo; + class AArch64TargetMachine : public LLVMTargetMachine { protected: std::unique_ptr TLOF; diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h index 2cb80a482d0..fdcc7e1ab7b 100644 --- a/lib/Target/X86/X86.h +++ b/lib/Target/X86/X86.h @@ -21,7 +21,10 @@ namespace llvm { class FunctionPass; class ImmutablePass; +class InstructionSelector; class PassRegistry; +class X86RegisterBankInfo; +class X86Subtarget; class X86TargetMachine; /// This pass converts a legalized DAG into a X86-specific DAG, ready for @@ -92,6 +95,9 @@ void initializeFixupBWInstPassPass(PassRegistry &); /// encoding when possible in order to reduce code size. FunctionPass *createX86EvexToVexInsts(); +InstructionSelector *createX86InstructionSelector(X86Subtarget &, + X86RegisterBankInfo &); + void initializeEvexToVexInstPassPass(PassRegistry &); } // End llvm namespace diff --git a/lib/Target/X86/X86InstructionSelector.cpp b/lib/Target/X86/X86InstructionSelector.cpp index 0f01bc4d1a8..d5a1a133f70 100644 --- a/lib/Target/X86/X86InstructionSelector.cpp +++ b/lib/Target/X86/X86InstructionSelector.cpp @@ -12,7 +12,6 @@ /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// -#include "X86InstructionSelector.h" #include "X86InstrBuilder.h" #include "X86InstrInfo.h" #include "X86RegisterBankInfo.h" @@ -23,7 +22,9 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/GlobalISel/InstructionSelector.h" #include "llvm/IR/Type.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" @@ -36,6 +37,47 @@ using namespace llvm; #error "You shouldn't build this" #endif +namespace { + +class X86InstructionSelector : public InstructionSelector { +public: + X86InstructionSelector(const X86Subtarget &STI, + const X86RegisterBankInfo &RBI); + + bool select(MachineInstr &I) const override; + +private: + /// tblgen-erated 'select' implementation, used as the initial selector for + /// the patterns that don't require complex C++. + bool selectImpl(MachineInstr &I) const; + + // TODO: remove after selectImpl support pattern with a predicate. + unsigned getFAddOp(LLT &Ty, const RegisterBank &RB) const; + unsigned getFSubOp(LLT &Ty, const RegisterBank &RB) const; + unsigned getAddOp(LLT &Ty, const RegisterBank &RB) const; + unsigned getSubOp(LLT &Ty, const RegisterBank &RB) const; + unsigned getLoadStoreOp(LLT &Ty, const RegisterBank &RB, unsigned Opc, + uint64_t Alignment) const; + + bool selectBinaryOp(MachineInstr &I, MachineRegisterInfo &MRI, + MachineFunction &MF) const; + bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI, + MachineFunction &MF) const; + bool selectFrameIndex(MachineInstr &I, MachineRegisterInfo &MRI, + MachineFunction &MF) const; + + const X86Subtarget &STI; + const X86InstrInfo &TII; + const X86RegisterInfo &TRI; + const X86RegisterBankInfo &RBI; + +#define GET_GLOBALISEL_TEMPORARIES_DECL +#include "X86GenGlobalISel.inc" +#undef GET_GLOBALISEL_TEMPORARIES_DECL +}; + +} // end anonymous namespace + #define GET_GLOBALISEL_IMPL #include "X86GenGlobalISel.inc" #undef GET_GLOBALISEL_IMPL @@ -415,3 +457,9 @@ bool X86InstructionSelector::selectFrameIndex(MachineInstr &I, return constrainSelectedInstRegOperands(I, TII, TRI, RBI); } + +InstructionSelector * +llvm::createX86InstructionSelector(X86Subtarget &Subtarget, + X86RegisterBankInfo &RBI) { + return new X86InstructionSelector(Subtarget, RBI); +} diff --git a/lib/Target/X86/X86InstructionSelector.h b/lib/Target/X86/X86InstructionSelector.h deleted file mode 100644 index fa258d4072f..00000000000 --- a/lib/Target/X86/X86InstructionSelector.h +++ /dev/null @@ -1,72 +0,0 @@ -//===- X86InstructionSelector --------------------------------*- C++ -*-==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -/// \file -/// This file declares the targeting of the InstructionSelector class for X86. -//===----------------------------------------------------------------------===// - -#ifdef LLVM_BUILD_GLOBAL_ISEL -#ifndef LLVM_LIB_TARGET_X86_X86INSTRUCTIONSELECTOR_H -#define LLVM_LIB_TARGET_X86_X86INSTRUCTIONSELECTOR_H - -#include "llvm/CodeGen/GlobalISel/InstructionSelector.h" -#include "llvm/CodeGen/MachineOperand.h" - -namespace llvm { - -class X86InstrInfo; -class X86RegisterBankInfo; -class X86RegisterInfo; -class X86Subtarget; -class X86TargetMachine; -class LLT; -class RegisterBank; -class MachineRegisterInfo; -class MachineFunction; - -class X86InstructionSelector : public InstructionSelector { -public: - X86InstructionSelector(const X86Subtarget &STI, - const X86RegisterBankInfo &RBI); - - bool select(MachineInstr &I) const override; - -private: - /// tblgen-erated 'select' implementation, used as the initial selector for - /// the patterns that don't require complex C++. - bool selectImpl(MachineInstr &I) const; - - // TODO: remove after selectImpl support pattern with a predicate. - unsigned getFAddOp(LLT &Ty, const RegisterBank &RB) const; - unsigned getFSubOp(LLT &Ty, const RegisterBank &RB) const; - unsigned getAddOp(LLT &Ty, const RegisterBank &RB) const; - unsigned getSubOp(LLT &Ty, const RegisterBank &RB) const; - unsigned getLoadStoreOp(LLT &Ty, const RegisterBank &RB, unsigned Opc, - uint64_t Alignment) const; - - bool selectBinaryOp(MachineInstr &I, MachineRegisterInfo &MRI, - MachineFunction &MF) const; - bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI, - MachineFunction &MF) const; - bool selectFrameIndex(MachineInstr &I, MachineRegisterInfo &MRI, - MachineFunction &MF) const; - - const X86Subtarget &STI; - const X86InstrInfo &TII; - const X86RegisterInfo &TRI; - const X86RegisterBankInfo &RBI; - -#define GET_GLOBALISEL_TEMPORARIES_DECL -#include "X86GenGlobalISel.inc" -#undef GET_GLOBALISEL_TEMPORARIES_DECL -}; - -} // end namespace llvm - -#endif // LLVM_LIB_TARGET_X86_X86INSTRUCTIONSELECTOR_H -#endif // LLVM_BUILD_GLOBAL_ISEL diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index a3148195076..03a1958121a 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -15,7 +15,6 @@ #include "X86.h" #include "X86CallLowering.h" #include "X86LegalizerInfo.h" -#include "X86InstructionSelector.h" #ifdef LLVM_BUILD_GLOBAL_ISEL #include "X86RegisterBankInfo.h" #endif @@ -287,8 +286,7 @@ X86TargetMachine::getSubtargetImpl(const Function &F) const { auto *RBI = new X86RegisterBankInfo(*I->getRegisterInfo()); GISel->RegBankInfo.reset(RBI); - GISel->InstSelector.reset(new X86InstructionSelector(*I, *RBI)); - + GISel->InstSelector.reset(createX86InstructionSelector(*I, *RBI)); #endif I->setGISelAccessor(*GISel); } diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index fd6d305b7d9..cf933f52604 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -25,6 +25,8 @@ namespace llvm { class StringRef; +class X86Subtarget; +class X86RegisterBankInfo; class X86TargetMachine final : public LLVMTargetMachine { std::unique_ptr TLOF; -- 2.50.1