From f018f9fea556677c15df970fd5b3f029136a715e Mon Sep 17 00:00:00 2001 From: Renato Golin Date: Wed, 23 Aug 2017 17:04:59 +0000 Subject: [PATCH] [ARM] more release notes updates for 5.0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@311578 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/ReleaseNotes.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst index 1fd523af2f7..f6ef4e0a3fa 100644 --- a/docs/ReleaseNotes.rst +++ b/docs/ReleaseNotes.rst @@ -82,14 +82,24 @@ Changes to the Arm Targets During this release the AArch64 target has: +* A much improved Global ISel at O0. +* Support for ARMv8.1 8.2 and 8.3 instructions. +* New scheduler information for ThunderX2. +* Some SVE type changes but not much more than that. * Made instruction fusion more aggressive, resulting in speedups for code making use of AArch64 AES instructions. AES fusion has been enabled for most Cortex-A cores and the AArch64MacroFusion pass was moved to the generic MacroFusion pass. * Added preferred function alignments for most Cortex-A cores. +* OpenMP "offload-to-self" base support. During this release the ARM target has: +* Improved, but still mostly broken, Global ISel. +* Scheduling models update, new schedule for Cortex-A57. +* Hardware breakpoint support in LLDB. +* New assembler error handling, with spelling corrections and multiple + suggestions on how to fix problems. * Improved mixed ARM/Thumb code generation. Some cases in which wrong relocations were emitted have been fixed. * Added initial support for mixed ARM/Thumb link-time optimization, using the -- 2.40.0