From ef2c5dd55cde3d740a906862f9c9c31415d1eccf Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Wed, 19 Oct 2016 15:55:09 +0000 Subject: [PATCH] TMP git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284604 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../llvm/CodeGen/GlobalISel/IRTranslator.h | 2 ++ lib/CodeGen/GlobalISel/IRTranslator.cpp | 33 +++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/include/llvm/CodeGen/GlobalISel/IRTranslator.h index 0bed9d12997..ad76cf8b6bc 100644 --- a/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -120,6 +120,8 @@ private: bool translateMemcpy(const CallInst &CI); + void getStackGuard(unsigned DstReg); + bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID); /// Translate call instruction. diff --git a/lib/CodeGen/GlobalISel/IRTranslator.cpp b/lib/CodeGen/GlobalISel/IRTranslator.cpp index 2a66251190c..94ef9673ab1 100644 --- a/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -382,6 +382,26 @@ bool IRTranslator::translateMemcpy(const CallInst &CI) { CallLowering::ArgInfo(0, CI.getType()), Args); } +void IRTranslator::getStackGuard(unsigned DstReg) { + auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD); + MIB.addDef(DstReg); + + auto &MF = MIRBuilder.getMF(); + auto &TLI = *MF.getSubtarget().getTargetLowering(); + Value *Global = TLI.getSDagStackGuard(*MF.getFunction()->getParent()); + if (!Global) + return; + + MachinePointerInfo MPInfo(Global); + MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1); + auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant | + MachineMemOperand::MODereferenceable; + *MemRefs = + MF.getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8, + DL->getPointerABIAlignment() / 8); + MIB.setMemRefs(MemRefs, MemRefs + 1); +} + bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID) { unsigned Op = 0; @@ -402,6 +422,19 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0); return true; } + case Intrinsic::stackguard: + getStackGuard(getOrCreateVReg(CI)); + return true; + case Intrinsic::stackprotector: { + // LLT PtrTy{*CI.getArgOperand(0).getType(), *DL}; + // unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy); + // getStackGuard(GuardVal); + + // AllocaInst *Slot = cast(I.getArgOperand(1)); + // unsigned StackSlot = MIRBuilder.buildFrameIndex(FrameReg, FI); + // MIRBuilder.buildStore(GuardVal, StackSlot); + return true; + } } LLT Ty{*CI.getOperand(0)->getType(), *DL}; -- 2.49.0