From eb02a3bc90575e32359bbac9fe269f5f57c62d04 Mon Sep 17 00:00:00 2001 From: Adhemerval Zanella Date: Thu, 16 May 2019 13:30:18 +0000 Subject: [PATCH] [AArch64] Handle ISD::LROUND and ISD::LLROUND This patch optimizes ISD::LROUND and ISD::LLROUND to fcvtas instruction. It currently only handles the scalar version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360894 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetSelectionDAG.td | 3 +++ lib/Target/AArch64/AArch64ISelLowering.cpp | 2 ++ lib/Target/AArch64/AArch64InstrInfo.td | 9 +++++++++ test/CodeGen/AArch64/llround-conv.ll | 12 ++++++++---- test/CodeGen/AArch64/lround-conv.ll | 12 ++++++++---- 5 files changed, 30 insertions(+), 8 deletions(-) diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index 64b07862713..6b1ef477bfa 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -450,6 +450,9 @@ def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>; +def lround : SDNode<"ISD::LROUND" , SDTFPToIntOp>; +def llround : SDNode<"ISD::LLROUND" , SDTFPToIntOp>; + def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 3ff4a225794..43620f150b6 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -457,6 +457,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setOperationAction(ISD::FMAXNUM, Ty, Legal); setOperationAction(ISD::FMINIMUM, Ty, Legal); setOperationAction(ISD::FMAXIMUM, Ty, Legal); + setOperationAction(ISD::LROUND, Ty, Legal); + setOperationAction(ISD::LLROUND, Ty, Legal); } if (Subtarget->hasFullFP16()) { diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td index 2c7124bcf9f..bf6be6761a9 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.td +++ b/lib/Target/AArch64/AArch64InstrInfo.td @@ -3083,6 +3083,15 @@ defm : FPToIntegerPats; defm : FPToIntegerPats; defm : FPToIntegerPats; +def : Pat<(i64 (lround f32:$Rn)), + (!cast(FCVTASUXSr) f32:$Rn)>; +def : Pat<(i64 (lround f64:$Rn)), + (!cast(FCVTASUXDr) f64:$Rn)>; +def : Pat<(i64 (llround f32:$Rn)), + (!cast(FCVTASUXSr) f32:$Rn)>; +def : Pat<(i64 (llround f64:$Rn)), + (!cast(FCVTASUXDr) f64:$Rn)>; + //===----------------------------------------------------------------------===// // Scaled integer to floating point conversion instructions. //===----------------------------------------------------------------------===// diff --git a/test/CodeGen/AArch64/llround-conv.ll b/test/CodeGen/AArch64/llround-conv.ll index a36af0820d5..797136037f0 100644 --- a/test/CodeGen/AArch64/llround-conv.ll +++ b/test/CodeGen/AArch64/llround-conv.ll @@ -1,7 +1,8 @@ ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s ; CHECK-LABEL: testmsws: -; CHECK: bl llroundf +; CHECK: fcvtas x0, s0 +; CHECK: ret define i32 @testmsws(float %x) { entry: %0 = tail call i64 @llvm.llround.f32(float %x) @@ -10,7 +11,8 @@ entry: } ; CHECK-LABEL: testmsxs: -; CHECK: b llroundf +; CHECK: fcvtas x0, s0 +; CHECK-NEXT: ret define i64 @testmsxs(float %x) { entry: %0 = tail call i64 @llvm.llround.f32(float %x) @@ -18,7 +20,8 @@ entry: } ; CHECK-LABEL: testmswd: -; CHECK: bl llround +; CHECK: fcvtas x0, d0 +; CHECK: ret define i32 @testmswd(double %x) { entry: %0 = tail call i64 @llvm.llround.f64(double %x) @@ -27,7 +30,8 @@ entry: } ; CHECK-LABEL: testmsxd: -; CHECK: b llround +; CHECK: fcvtas x0, d0 +; CHECK-NEXT: ret define i64 @testmsxd(double %x) { entry: %0 = tail call i64 @llvm.llround.f64(double %x) diff --git a/test/CodeGen/AArch64/lround-conv.ll b/test/CodeGen/AArch64/lround-conv.ll index 483454a02f4..678d3149f20 100644 --- a/test/CodeGen/AArch64/lround-conv.ll +++ b/test/CodeGen/AArch64/lround-conv.ll @@ -1,7 +1,8 @@ ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s ; CHECK-LABEL: testmsws: -; CHECK: bl lroundf +; CHECK: fcvtas x0, s0 +; CHECK: ret define i32 @testmsws(float %x) { entry: %0 = tail call i64 @llvm.lround.i64.f32(float %x) @@ -10,7 +11,8 @@ entry: } ; CHECK-LABEL: testmsxs: -; CHECK: b lroundf +; CHECK: fcvtas x0, s0 +; CHECK-NEXT: ret define i64 @testmsxs(float %x) { entry: %0 = tail call i64 @llvm.lround.i64.f32(float %x) @@ -18,7 +20,8 @@ entry: } ; CHECK-LABEL: testmswd: -; CHECK: bl lround +; CHECK: fcvtas x0, d0 +; CHECK: ret define i32 @testmswd(double %x) { entry: %0 = tail call i64 @llvm.lround.i64.f64(double %x) @@ -27,7 +30,8 @@ entry: } ; CHECK-LABEL: testmsxd: -; CHECK: b lround +; CHECK: fcvtas x0, d0 +; CHECK-NEXT: ret define i64 @testmsxd(double %x) { entry: %0 = tail call i64 @llvm.lround.i64.f64(double %x) -- 2.40.0