From ea24d1dabd6a18d261b450df5af9ddd9aec89c68 Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Mon, 3 Jun 2019 08:49:17 +0000 Subject: [PATCH] [AArch64] Check for simple type in FPToUInt DAGCombiner was hitting a SimpleType assertion when trying to combine a v3f32 before type legalization. bugzilla: https://bugs.llvm.org/show_bug.cgi?id=41916 Differential Revision: https://reviews.llvm.org/D62734 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362365 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64ISelLowering.cpp | 3 +++ test/CodeGen/AArch64/v3f-to-int.ll | 17 +++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 test/CodeGen/AArch64/v3f-to-int.ll diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index d8e52929ffb..ba8bbd25159 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -9206,6 +9206,9 @@ static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG, if (!Subtarget->hasNEON()) return SDValue(); + if (!N->getValueType(0).isSimple()) + return SDValue(); + SDValue Op = N->getOperand(0); if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() || Op.getOpcode() != ISD::FMUL) diff --git a/test/CodeGen/AArch64/v3f-to-int.ll b/test/CodeGen/AArch64/v3f-to-int.ll new file mode 100644 index 00000000000..9c9dd5ed7e9 --- /dev/null +++ b/test/CodeGen/AArch64/v3f-to-int.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=aarch64--linux-eabi %s -o - | FileCheck %s + +; CHECK-LABEL: convert_v3f32 +; CHECK: strb +; CHECK: strh +define void @convert_v3f32() { +entry: + br label %bb + +bb: + %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <3 x i32> + %1 = fmul reassoc nnan ninf nsz contract afn <3 x float> %0, + %2 = fptoui <3 x float> %1 to <3 x i8> + %3 = bitcast i8* undef to <3 x i8>* + store <3 x i8> %2, <3 x i8>* %3, align 1 + ret void +} -- 2.40.0