From e7c6ff09d78be5d0733660936192cd5a01e2e55c Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Wed, 11 Oct 2017 18:04:41 +0000 Subject: [PATCH] [NFC] update test case so checks are not order dependent when not needed git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315482 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/PowerPC/sjlj.ll | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll index 984f9d9f6f5..14aec583891 100644 --- a/test/CodeGen/PowerPC/sjlj.ll +++ b/test/CodeGen/PowerPC/sjlj.ll @@ -60,7 +60,7 @@ return: ; preds = %if.end, %if.then ; FIXME: We should be saving VRSAVE on Darwin, but we're not! -; CHECK: @main +; CHECK-LABEL: main: ; CHECK: std ; Make sure that we're not saving VRSAVE on non-Darwin: ; CHECK-NOT: mfspr @@ -87,12 +87,12 @@ return: ; preds = %if.end, %if.then ; CHECK: .LBB1_5: -; CHECK: lfd -; CHECK: lxvd2x +; CHECK-DAG: lfd +; CHECK-DAG: lxvd2x ; CHECK: ld ; CHECK: blr -; CHECK-NOAV: @main +; CHECK-NOAV-LABEL: main: ; CHECK-NOAV-NOT: stxvd2x ; CHECK-NOAV: bcl ; CHECK-NOAV: mflr @@ -131,7 +131,7 @@ return: ; preds = %if.end, %if.then %3 = load i32, i32* %retval ret i32 %3 -; CHECK: @main2 +; CHECK-LABEL: main2: ; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha ; CHECK-DAG: std 31, env_sigill@toc@l([[REG]]) -- 2.50.1