From e7c439738d220450a8bc752e1f55841cf6adfab9 Mon Sep 17 00:00:00 2001 From: Alexander Timofeev Date: Mon, 27 May 2019 15:03:29 +0000 Subject: [PATCH] [AMDGPU] Fix for the address sanitizer failure caused by the ifollowing commit: 1a8b2ea611cf4ca7cb09562e0238cfefa27c05b5 Divergence driven ISel. Assign register class for cross block values according to the divergence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361770 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index 8ad7a52c92b..4fd28fc6d81 100644 --- a/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -595,7 +595,9 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { unsigned OpNo = UseMI->getOperandNo(&Use); const MCInstrDesc &Desc = TII->get(UseMI->getOpcode()); - if (Desc.OpInfo && Desc.OpInfo[OpNo].RegClass != -1) { + if (!Desc.isPseudo() && Desc.OpInfo && + OpNo <= Desc.getNumOperands() && + Desc.OpInfo[OpNo].RegClass != -1) { const TargetRegisterClass *OpRC = TRI->getRegClass(Desc.OpInfo[OpNo].RegClass); if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass && -- 2.40.0