From e675164b4b17d6840c0cbb970bf365a447f31f08 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 20 Dec 2018 00:37:02 +0000 Subject: [PATCH] AMDGPU/GlobalISel: RegBankSelect for fp conversions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349709 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 6 ++++ lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 3 ++ .../AMDGPU/GlobalISel/legalize-fptrunc.mir | 17 ++++++++++ .../GlobalISel/regbankselect-fptrunc.mir | 31 +++++++++++++++++++ .../GlobalISel/regbankselect-sitofp.mir | 31 +++++++++++++++++++ .../GlobalISel/regbankselect-uitofp.mir | 31 +++++++++++++++++++ 6 files changed, 119 insertions(+) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir diff --git a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 4884dbb2b95..cac53d9cc87 100644 --- a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -96,6 +96,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST, { G_FADD, G_FMUL, G_FNEG, G_FABS, G_FMA}) .legalFor({S32, S64}); + getActionDefinitionsBuilder(G_FPTRUNC) + .legalFor({{S32, S64}}); + // Use actual fsub instruction setAction({G_FSUB, S32}, Legal); @@ -121,6 +124,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST, setAction({G_SITOFP, S32}, Legal); setAction({G_SITOFP, 1, S32}, Legal); + setAction({G_UITOFP, S32}, Legal); + setAction({G_UITOFP, 1, S32}, Legal); + setAction({G_FPTOUI, S32}, Legal); setAction({G_FPTOUI, 1, S32}, Legal); diff --git a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 10533daa24f..bf218f7c4b9 100644 --- a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -374,6 +374,9 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case AMDGPU::G_FPTOUI: case AMDGPU::G_FMUL: case AMDGPU::G_FMA: + case AMDGPU::G_SITOFP: + case AMDGPU::G_UITOFP: + case AMDGPU::G_FPTRUNC: return getDefaultMappingVOP(MI); case AMDGPU::G_IMPLICIT_DEF: { unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir new file mode 100644 index 00000000000..40eae268917 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir @@ -0,0 +1,17 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- +name: test_fptrunc_f64_to_f32 +body: | + bb.0: + liveins: $vgpr0_vgpr1 + + ; CHECK-LABEL: name: test_fptrunc_f64_to_f32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[COPY]](s64) + ; CHECK: $vgpr0 = COPY [[FPTRUNC]](s32) + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(s32) = G_FPTRUNC %0 + $vgpr0 = COPY %1 +... diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir new file mode 100644 index 00000000000..02cb49a4b8f --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- +name: fptrunc_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1 + ; CHECK-LABEL: name: fptrunc_s + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 + ; CHECK: [[FPTRUNC:%[0-9]+]]:vgpr(s32) = G_FPTRUNC [[COPY]](s64) + %0:_(s64) = COPY $sgpr0_sgpr1 + %1:_(s32) = G_FPTRUNC %0 +... + +--- +name: fptrunc_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1 + ; CHECK-LABEL: name: fptrunc_v + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 + ; CHECK: [[FPTRUNC:%[0-9]+]]:vgpr(s32) = G_FPTRUNC [[COPY]](s64) + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(s32) = G_FPTRUNC %0 +... diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir new file mode 100644 index 00000000000..e48292127d5 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- +name: sitofp_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + ; CHECK-LABEL: name: sitofp_s + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[SITOFP:%[0-9]+]]:vgpr(s32) = G_SITOFP [[COPY]](s32) + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = G_SITOFP %0 +... + +--- +name: sitofp_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: sitofp_v + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[SITOFP:%[0-9]+]]:vgpr(s32) = G_SITOFP [[COPY]](s32) + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_SITOFP %0 +... diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir new file mode 100644 index 00000000000..07f47c559a7 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- +name: uitofp_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + ; CHECK-LABEL: name: uitofp_s + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[UITOFP:%[0-9]+]]:vgpr(s32) = G_UITOFP [[COPY]](s32) + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = G_UITOFP %0 +... + +--- +name: uitofp_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: uitofp_v + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[UITOFP:%[0-9]+]]:vgpr(s32) = G_UITOFP [[COPY]](s32) + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_UITOFP %0 +... -- 2.50.1