From e5fe899c4b578e2ecf4820738d15dffff5efe291 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Mon, 16 Sep 2019 23:46:03 +0000 Subject: [PATCH] [GlobalISel] Partially revert r371901. r371901 was overeager and widenScalarDst() and the like in the legalizer attempt to increment the insert point given in order to add new instructions after the currently legalizing inst. In cases where the insertion point is not exactly the current instruction, then callers need to de-compensate for the behaviour by decrementing the insertion iterator before calling them. It's not a nice state of affairs, for now just undo the problematic parts of the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372050 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 4 +- .../legalize-phi-insertpt-decrement.mir | 99 +++++++++++++++++++ .../AMDGPU/GlobalISel/legalize-phi.mir | 2 +- 3 files changed, 102 insertions(+), 3 deletions(-) create mode 100644 test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir diff --git a/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 8c356c62a17..d4ae3b52a46 100644 --- a/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -1765,7 +1765,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { } MachineBasicBlock &MBB = *MI.getParent(); - MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI()); + MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); widenScalarDst(MI, WideTy); Observer.changedInstr(MI); return Legalized; @@ -3156,7 +3156,7 @@ LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, } MachineBasicBlock &MBB = *MI.getParent(); - MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI()); + MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); moreElementsVectorDst(MI, MoreTy, 0); Observer.changedInstr(MI); return Legalized; diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir b/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir new file mode 100644 index 00000000000..87db6070214 --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir @@ -0,0 +1,99 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s +--- | + target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + + define void @snork() { + bb: + br label %bb1 + + bb1: ; preds = %bb3, %bb + %lsr.iv = phi i16* [ %scevgep, %bb3 ], [ undef, %bb ] + %tmp = phi i1 [ %tmp9, %bb3 ], [ undef, %bb ] + br i1 %tmp, label %bb10, label %bb3 + + bb3: ; preds = %bb1 + %tmp5 = getelementptr i16, i16* null, i64 2 + %tmp6 = load i16, i16* %lsr.iv, align 2, !tbaa !0 + %tmp7 = icmp eq i16 %tmp6, -1 + %tmp8 = load i16, i16* %tmp5, align 2, !tbaa !0 + %tmp9 = icmp eq i16 %tmp8, -1 + %scevgep = getelementptr i16, i16* %lsr.iv, i64 2 + br i1 %tmp7, label %bb10, label %bb1 + + bb10: ; preds = %bb3, %bb1 + ret void + } + + !0 = !{!1, !1, i64 0} + !1 = !{!"short", !2, i64 0} + !2 = !{!"omnipotent char", !3, i64 0} + !3 = !{!"Simple C/C++ TBAA"} + +... +--- +name: snork +alignment: 16 +tracksRegLiveness: true +frameInfo: + maxAlignment: 1 +body: | + ; CHECK-LABEL: name: snork + ; CHECK: bb.0.bb: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64) + ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF + ; CHECK: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF + ; CHECK: bb.1.bb1: + ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK: [[PHI:%[0-9]+]]:_(p0) = G_PHI %6(p0), %bb.2, [[DEF]](p0), %bb.0 + ; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI %20(s16), %bb.2, [[DEF1]](s16), %bb.0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[PHI1]](s16) + ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.3 + ; CHECK: bb.2.bb3: + ; CHECK: successors: %bb.3(0x40000000), %bb.1(0x40000000) + ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[INTTOPTR]], [[C1]](s64) + ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PHI]](p0) :: (load 2 from %ir.lsr.iv) + ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s16) + ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT]](s32), [[C2]] + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32) + ; CHECK: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[GEP]](p0) :: (load 2 from %ir.tmp5) + ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16) + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32) + ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT1]](s32), [[COPY]] + ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[PHI]], [[C1]](s64) + ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ICMP1]](s32) + ; CHECK: G_BRCOND [[TRUNC1]](s1), %bb.3 + ; CHECK: G_BR %bb.1 + ; CHECK: bb.3.bb10: + ; CHECK: RET 0 + bb.1.bb: + %3:_(s64) = G_CONSTANT i64 0 + %2:_(p0) = G_INTTOPTR %3(s64) + %7:_(s16) = G_CONSTANT i16 -1 + %12:_(p0) = G_IMPLICIT_DEF + %13:_(s1) = G_IMPLICIT_DEF + + bb.2.bb1: + %0:_(p0) = G_PHI %11(p0), %bb.3, %12(p0), %bb.1 + %1:_(s1) = G_PHI %10(s1), %bb.3, %13(s1), %bb.1 + G_BRCOND %1(s1), %bb.4 + + bb.3.bb3: + %4:_(s64) = G_CONSTANT i64 4 + %5:_(p0) = G_GEP %2, %4(s64) + %6:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.lsr.iv) + %8:_(s1) = G_ICMP intpred(eq), %6(s16), %7 + %9:_(s16) = G_LOAD %5(p0) :: (load 2 from %ir.tmp5) + %10:_(s1) = G_ICMP intpred(eq), %9(s16), %7 + %11:_(p0) = G_GEP %0, %4(s64) + G_BRCOND %8(s1), %bb.4 + G_BR %bb.2 + + bb.4.bb10: + RET 0 + +... diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir index 24b144c376a..f17323cdd3f 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir @@ -160,8 +160,8 @@ body: | ; CHECK: G_BR %bb.2 ; CHECK: bb.2: ; CHECK: [[PHI:%[0-9]+]]:_(<4 x s16>) = G_PHI [[INSERT]](<4 x s16>), %bb.0, [[INSERT3]](<4 x s16>), %bb.1 - ; CHECK: [[DEF4:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[PHI]](<4 x s16>), 0 + ; CHECK: [[DEF4:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[INSERT4:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF4]], [[EXTRACT1]](<3 x s16>), 0 ; CHECK: $vgpr0_vgpr1 = COPY [[INSERT4]](<4 x s16>) ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31 -- 2.40.0