From e5a2b43b652b2a75cd3f22c95210bea20bede9aa Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 25 Feb 2019 21:05:09 +0000 Subject: [PATCH] [LangRef] *.overflow intrinsics now support vectors We have all the necessary legalization, expansion and unrolling support required for the *.overflow intrinsics with vector types, so update the docs to make that clear. Note: vectorization is not in place yet (the non-homogenous return types aren't well supported) so we still must explicitly use the vectors intrinsics and not reply on slp/loop. Differential Revision: https://reviews.llvm.org/D58618 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354821 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/LangRef.rst | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/docs/LangRef.rst b/docs/LangRef.rst index 8483d74dd4f..6af6ddfb3f2 100644 --- a/docs/LangRef.rst +++ b/docs/LangRef.rst @@ -12641,13 +12641,14 @@ Syntax: """"""" This is an overloaded intrinsic. You can use ``llvm.sadd.with.overflow`` -on any integer bit width. +on any integer bit width or vectors of integers. :: declare {i16, i1} @llvm.sadd.with.overflow.i16(i16 %a, i16 %b) declare {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) declare {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) + declare {<4 x i32>, <4 x i1>} @llvm.sadd.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) Overview: """"""""" @@ -12691,13 +12692,14 @@ Syntax: """"""" This is an overloaded intrinsic. You can use ``llvm.uadd.with.overflow`` -on any integer bit width. +on any integer bit width or vectors of integers. :: declare {i16, i1} @llvm.uadd.with.overflow.i16(i16 %a, i16 %b) declare {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) declare {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) + declare {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) Overview: """"""""" @@ -12740,13 +12742,14 @@ Syntax: """"""" This is an overloaded intrinsic. You can use ``llvm.ssub.with.overflow`` -on any integer bit width. +on any integer bit width or vectors of integers. :: declare {i16, i1} @llvm.ssub.with.overflow.i16(i16 %a, i16 %b) declare {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) declare {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) + declare {<4 x i32>, <4 x i1>} @llvm.ssub.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) Overview: """"""""" @@ -12790,13 +12793,14 @@ Syntax: """"""" This is an overloaded intrinsic. You can use ``llvm.usub.with.overflow`` -on any integer bit width. +on any integer bit width or vectors of integers. :: declare {i16, i1} @llvm.usub.with.overflow.i16(i16 %a, i16 %b) declare {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b) declare {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b) + declare {<4 x i32>, <4 x i1>} @llvm.usub.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) Overview: """"""""" @@ -12840,13 +12844,14 @@ Syntax: """"""" This is an overloaded intrinsic. You can use ``llvm.smul.with.overflow`` -on any integer bit width. +on any integer bit width or vectors of integers. :: declare {i16, i1} @llvm.smul.with.overflow.i16(i16 %a, i16 %b) declare {i32, i1} @llvm.smul.with.overflow.i32(i32 %a, i32 %b) declare {i64, i1} @llvm.smul.with.overflow.i64(i64 %a, i64 %b) + declare {<4 x i32>, <4 x i1>} @llvm.smul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) Overview: """"""""" @@ -12890,13 +12895,14 @@ Syntax: """"""" This is an overloaded intrinsic. You can use ``llvm.umul.with.overflow`` -on any integer bit width. +on any integer bit width or vectors of integers. :: declare {i16, i1} @llvm.umul.with.overflow.i16(i16 %a, i16 %b) declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b) declare {i64, i1} @llvm.umul.with.overflow.i64(i64 %a, i64 %b) + declare {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) Overview: """"""""" -- 2.40.0