From e584761c22875f38f40a2d63891768e4baf014bd Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 21 Mar 2019 20:45:36 +0000 Subject: [PATCH] GlobalISel: Fix RegBankSelect for REG_SEQUENCE The AArch64 test was broken since the result register already had a set register class, so this test was a no-op. The mapping verify call would fail because the result size is not the same as the inputs like in a copy or phi. The AMDGPU testcases are half broken and introduce illegal VGPR->SGPR copies which need much more work to handle correctly (same for phis), but add them as a baseline. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356713 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 20 ++- .../GlobalISel/regbankselect-reg_sequence.mir | 11 +- .../GlobalISel/regbankselect-reg-sequence.mir | 140 ++++++++++++++++++ 3 files changed, 160 insertions(+), 11 deletions(-) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir diff --git a/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp index 1b639945293..55f10a2d065 100644 --- a/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ b/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -207,11 +207,23 @@ RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const { continue; } } - const ValueMapping *ValMapping = - &getValueMapping(0, getSizeInBits(Reg, MRI, TRI), *CurRegBank); + + unsigned Size = getSizeInBits(Reg, MRI, TRI); + const ValueMapping *ValMapping = &getValueMapping(0, Size, *CurRegBank); if (IsCopyLike) { - OperandsMapping[0] = ValMapping; - CompleteMapping = true; + if (!OperandsMapping[0]) { + if (MI.isRegSequence()) { + // For reg_sequence, the result size does not match the input. + unsigned ResultSize = getSizeInBits(MI.getOperand(0).getReg(), + MRI, TRI); + OperandsMapping[0] = &getValueMapping(0, ResultSize, *CurRegBank); + } else { + OperandsMapping[0] = ValMapping; + } + + CompleteMapping = true; + } + break; } OperandsMapping[OpIdx] = ValMapping; diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir index 32a0d4335c7..7c66c019b73 100644 --- a/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir +++ b/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir @@ -1,7 +1,4 @@ # RUN: llc %s -mtriple aarch64-- -o - -run-pass regbankselect | FileCheck %s ---- | - define void @foo() { ret void } -... --- # CHECK-LABEL: foo # Check that we produce a valid mapping for REG_SEQUENCE. @@ -10,16 +7,16 @@ # whereas since REG_SEQUENCE are kind of target opcode # their definition may not have a type. # -# CHECK: id: 0, class: dd + +# CHECK: %0:fpr(s128) = REG_SEQUENCE $d0, %subreg.dsub0, $d1, %subreg.dsub1 + name: foo legalized: true tracksRegLiveness: true -registers: - - { id: 0, class: dd } body: | bb.0: liveins: $d0, $d1 - %0 = REG_SEQUENCE $d0, %subreg.dsub0, $d1, %subreg.dsub1 + %0:_(s128) = REG_SEQUENCE $d0, %subreg.dsub0, $d1, %subreg.dsub1 ... diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir new file mode 100644 index 00000000000..efaaebfc9d6 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir @@ -0,0 +1,140 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- +name: reg_sequence_ss_vreg +legalized: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $sgpr0, $sgpr1 + + ; CHECK-LABEL: name: reg_sequence_ss_vreg + ; CHECK: liveins: $sgpr0, $sgpr1 + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = COPY $sgpr1 + %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 +... + +--- +name: reg_sequence_ss_physreg +legalized: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $sgpr0, $sgpr1 + + ; CHECK-LABEL: name: reg_sequence_ss_physreg + ; CHECK: liveins: $sgpr0, $sgpr1 + ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1 + %0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1 +... + +--- +name: reg_sequence_sv_vreg +legalized: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $sgpr0, $vgpr0 + + ; CHECK-LABEL: name: reg_sequence_sv_vreg + ; CHECK: liveins: $sgpr0, $vgpr0 + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = COPY $vgpr0 + %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 +... + +--- +name: reg_sequence_sv_physreg +legalized: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $sgpr0, $vgpr0 + + ; CHECK-LABEL: name: reg_sequence_sv_physreg + ; CHECK: liveins: $sgpr0, $vgpr0 + ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1 + %0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1 +... + +--- +name: reg_sequence_vs_vreg +legalized: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $sgpr0 + + ; CHECK-LABEL: name: reg_sequence_vs_vreg + ; CHECK: liveins: $vgpr0, $sgpr0 + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $sgpr0 + %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 +... + +--- +name: reg_sequence_vs_physreg +legalized: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $sgpr0 + + ; CHECK-LABEL: name: reg_sequence_vs_physreg + ; CHECK: liveins: $vgpr0, $sgpr0 + ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $sgpr0, %subreg.sub1 + %0:_(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $sgpr0, %subreg.sub1 +... + +--- +name: reg_sequence_vv_vreg +legalized: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + + ; CHECK-LABEL: name: reg_sequence_vv_vreg + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 +... + +--- +name: reg_sequence_vv_physreg +legalized: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + + ; CHECK-LABEL: name: reg_sequence_vv_physreg + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $vgpr1, %subreg.sub1 + %0:_(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $vgpr1, %subreg.sub1 +... + -- 2.50.1