From e4756450e1e5346cd6b30b19264b54b69dd0bee1 Mon Sep 17 00:00:00 2001 From: "Duncan P. N. Exon Smith" Date: Thu, 30 Jun 2016 23:04:51 +0000 Subject: [PATCH] CodeGen: Use MachineInstr& in IfConversion, NFC Switch to a range-based for in IfConverter::PredicateBlock and take MachineInstr& in MaySpeculate to avoid an implicit conversion from MachineBasicBlock::iterator to MachineInstr*. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274290 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/IfConversion.cpp | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp index 4cdad607f76..ed5eb05299d 100644 --- a/lib/CodeGen/IfConversion.cpp +++ b/lib/CodeGen/IfConversion.cpp @@ -1588,14 +1588,14 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind, return true; } -static bool MaySpeculate(const MachineInstr *MI, +static bool MaySpeculate(const MachineInstr &MI, SmallSet &LaterRedefs) { bool SawStore = true; - if (!MI->isSafeToMove(nullptr, SawStore)) + if (!MI.isSafeToMove(nullptr, SawStore)) return false; - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - const MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI.getOperand(i); if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); @@ -1616,8 +1616,8 @@ void IfConverter::PredicateBlock(BBInfo &BBI, SmallSet *LaterRedefs) { bool AnyUnpred = false; bool MaySpec = LaterRedefs != nullptr; - for (MachineBasicBlock::iterator I = BBI.BB->begin(); I != E; ++I) { - if (I->isDebugValue() || TII->isPredicated(*I)) + for (MachineInstr &I : llvm::make_range(BBI.BB->begin(), E)) { + if (I.isDebugValue() || TII->isPredicated(I)) continue; // It may be possible not to predicate an instruction if it's the 'true' // side of a diamond and the 'false' side may re-define the instruction's @@ -1629,16 +1629,16 @@ void IfConverter::PredicateBlock(BBInfo &BBI, // If any instruction is predicated, then every instruction after it must // be predicated. MaySpec = false; - if (!TII->PredicateInstruction(*I, Cond)) { + if (!TII->PredicateInstruction(I, Cond)) { #ifndef NDEBUG - dbgs() << "Unable to predicate " << *I << "!\n"; + dbgs() << "Unable to predicate " << I << "!\n"; #endif llvm_unreachable(nullptr); } // If the predicated instruction now redefines a register as the result of // if-conversion, add an implicit kill. - UpdatePredRedefs(*I, Redefs); + UpdatePredRedefs(I, Redefs); } BBI.Predicate.append(Cond.begin(), Cond.end()); -- 2.50.0