From e3b8cd6b612b5a8302f3b42a9855b5b4dffd114f Mon Sep 17 00:00:00 2001 From: Hiroshi Inoue Date: Sun, 16 Jul 2017 08:11:56 +0000 Subject: [PATCH] fix typos in comments; NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308127 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 2 +- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 2 +- lib/Target/X86/X86FixupBWInsts.cpp | 2 +- test/CodeGen/AMDGPU/parallelandifcollapse.ll | 2 +- test/CodeGen/AMDGPU/parallelorifcollapse.ll | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 631420589fc..258b1737deb 100644 --- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -885,7 +885,7 @@ CCAssignFn *AMDGPUCallLowering::CCAssignFnForReturn(CallingConv::ID CC, /// When the SelectionDAGBuilder computes the Ins, it takes care of splitting /// input values across multiple registers. Each item in the Ins array -/// represents a single value that will be stored in regsters. Ins[x].VT is +/// represents a single value that will be stored in registers. Ins[x].VT is /// the value type of the value that will be stored in the register, so /// whatever SDNode we lower the argument to needs to be this type. /// diff --git a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index e3c90f25060..b37c274102b 100644 --- a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -1208,7 +1208,7 @@ bool AMDGPUOperand::isInlinableImm(MVT type) const { } bool AMDGPUOperand::isLiteralImm(MVT type) const { - // Check that this imediate can be added as literal + // Check that this immediate can be added as literal if (!isImmTy(ImmTyNone)) { return false; } diff --git a/lib/Target/X86/X86FixupBWInsts.cpp b/lib/Target/X86/X86FixupBWInsts.cpp index c28746f9643..95c6f2a3fa3 100644 --- a/lib/Target/X86/X86FixupBWInsts.cpp +++ b/lib/Target/X86/X86FixupBWInsts.cpp @@ -22,7 +22,7 @@ /// instructions and register-to-register moves. It would /// seem like cmov(s) would also be affected, but because of the way cmov is /// really implemented by most machines as reading both the destination and -/// and source regsters, and then "merging" the two based on a condition, +/// and source registers, and then "merging" the two based on a condition, /// it really already should be considered as having a true dependence on the /// destination register as well. /// diff --git a/test/CodeGen/AMDGPU/parallelandifcollapse.ll b/test/CodeGen/AMDGPU/parallelandifcollapse.ll index 190d2b72eba..87f37144244 100644 --- a/test/CodeGen/AMDGPU/parallelandifcollapse.ll +++ b/test/CodeGen/AMDGPU/parallelandifcollapse.ll @@ -8,7 +8,7 @@ ; CHECK-NEXT: OR_INT ; FIXME: For some reason having the allocas here allowed the flatten cfg pass -; to do its transfomation, however now that we are using local memory for +; to do its transformation, however now that we are using local memory for ; allocas, the transformation isn't happening. define amdgpu_kernel void @_Z9chk1D_512v() #0 { diff --git a/test/CodeGen/AMDGPU/parallelorifcollapse.ll b/test/CodeGen/AMDGPU/parallelorifcollapse.ll index 91116b0f65e..e199d5b5df2 100644 --- a/test/CodeGen/AMDGPU/parallelorifcollapse.ll +++ b/test/CodeGen/AMDGPU/parallelorifcollapse.ll @@ -5,7 +5,7 @@ ; then merge if-regions with the same bodies. ; FIXME: For some reason having the allocas here allowed the flatten cfg pass -; to do its transfomation, however now that we are using local memory for +; to do its transformation, however now that we are using local memory for ; allocas, the transformation isn't happening. ; XFAIL: * ; -- 2.50.1