From dfc99b073dad01e1136b9e3c7fae55d63fa931eb Mon Sep 17 00:00:00 2001 From: Peter Johnson Date: Wed, 18 Jan 2006 02:20:06 +0000 Subject: [PATCH] x86id.re: Fix #66 (fstp generated invalid opcode). Cleaned up fldstpt_insn a bit as well. We were testing this but for some reason didn't check the "golden" outputs for correctness. svn path=/trunk/yasm/; revision=1338 --- modules/arch/x86/tests/gas64/gas-fp.hex | 2 +- modules/arch/x86/tests/genopcode.hex | 2 +- modules/arch/x86/x86id.re | 30 ++++++++++++++++--------- 3 files changed, 22 insertions(+), 12 deletions(-) diff --git a/modules/arch/x86/tests/gas64/gas-fp.hex b/modules/arch/x86/tests/gas64/gas-fp.hex index f61bb837..cfea2727 100644 --- a/modules/arch/x86/tests/gas64/gas-fp.hex +++ b/modules/arch/x86/tests/gas64/gas-fp.hex @@ -136,7 +136,7 @@ db 00 00 00 -d9 +dd d9 d9 1c diff --git a/modules/arch/x86/tests/genopcode.hex b/modules/arch/x86/tests/genopcode.hex index 831f4cd7..4814eb28 100644 --- a/modules/arch/x86/tests/genopcode.hex +++ b/modules/arch/x86/tests/genopcode.hex @@ -318,7 +318,7 @@ d9 1e 00 00 -d9 +dd dc df 06 diff --git a/modules/arch/x86/x86id.re b/modules/arch/x86/x86id.re index 10b1de78..1d7deb35 100644 --- a/modules/arch/x86/x86id.re +++ b/modules/arch/x86/x86id.re @@ -1403,19 +1403,29 @@ static const x86_insn_info sldtmsw_insn[] = { }; /* Floating point instructions - load/store with pop (integer and normal) */ -static const x86_insn_info fldstp_insn[] = { - { CPU_FPU, MOD_Gap0|MOD_SpAdd|MOD_GasSufS, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, +static const x86_insn_info fld_insn[] = { + { CPU_FPU, MOD_GasSufS, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, {OPT_Mem|OPS_32|OPA_EA, 0, 0} }, - { CPU_FPU, MOD_Gap0|MOD_SpAdd|MOD_GasSufL, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, + { CPU_FPU, MOD_GasSufL, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, {OPT_Mem|OPS_64|OPA_EA, 0, 0} }, - { CPU_FPU, MOD_Gap0|MOD_Gap1|MOD_SpAdd, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, + { CPU_FPU, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 5, 1, {OPT_Mem|OPS_80|OPA_EA, 0, 0} }, - { CPU_FPU, MOD_Op1Add, 0, 0, 0, 2, {0xD9, 0x00, 0}, 0, 1, + { CPU_FPU, 0, 0, 0, 0, 2, {0xD9, 0xC0, 0}, 0, 1, + {OPT_Reg|OPS_80|OPA_Op1Add, 0, 0} } +}; +static const x86_insn_info fstp_insn[] = { + { CPU_FPU, MOD_GasSufS, 0, 0, 0, 1, {0xD9, 0, 0}, 3, 1, + {OPT_Mem|OPS_32|OPA_EA, 0, 0} }, + { CPU_FPU, MOD_GasSufL, 0, 0, 0, 1, {0xDD, 0, 0}, 3, 1, + {OPT_Mem|OPS_64|OPA_EA, 0, 0} }, + { CPU_FPU, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 7, 1, + {OPT_Mem|OPS_80|OPA_EA, 0, 0} }, + { CPU_FPU, 0, 0, 0, 0, 2, {0xDD, 0xD8, 0}, 0, 1, {OPT_Reg|OPS_80|OPA_Op1Add, 0, 0} } }; /* Long memory version of floating point load/store for GAS */ static const x86_insn_info fldstpt_insn[] = { - { CPU_FPU, MOD_Gap0|MOD_Gap1|MOD_SpAdd, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, + { CPU_FPU, MOD_SpAdd, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, {OPT_Mem|OPS_80|OPA_EA, 0, 0} } }; static const x86_insn_info fildstp_insn[] = { @@ -4135,20 +4145,20 @@ yasm_x86__parse_check_insn(yasm_arch *arch, unsigned long data[4], 'verr' W? { RET_INSN(4, prot286, 0x0400, CPU_286|CPU_Prot); } 'verw' W? { RET_INSN(4, prot286, 0x0500, CPU_286|CPU_Prot); } /* Floating point instructions */ - 'fld' [lLsS]? { RET_INSN(3, fldstp, 0x0500C0, CPU_FPU); } + 'fld' [lLsS]? { RET_INSN(3, fld, 0, CPU_FPU); } 'fldt' { data[3] |= 0x80 << 8; - RET_INSN_GAS(4, fldstpt, 0x0500C0, CPU_FPU); + RET_INSN_GAS(4, fldstpt, 0x05, CPU_FPU); } 'fild' [lLqQsS]? { RET_INSN(4, fildstp, 0x050200, CPU_FPU); } 'fildll' { RET_INSN_GAS(6, fbldstp, 0x05, CPU_FPU); } 'fbld' { RET_INSN(4, fbldstp, 0x04, CPU_FPU); } 'fst' [lLsS]? { RET_INSN(3, fst, 0, CPU_FPU); } 'fist' [lLsS]? { RET_INSN(4, fiarith, 0x02DB, CPU_FPU); } - 'fstp' [lLsS]? { RET_INSN(4, fldstp, 0x0703D8, CPU_FPU); } + 'fstp' [lLsS]? { RET_INSN(4, fstp, 0, CPU_FPU); } 'fstpt' { data[3] |= 0x80 << 8; - RET_INSN_GAS(5, fldstpt, 0x0703D8, CPU_FPU); + RET_INSN_GAS(5, fldstpt, 0x07, CPU_FPU); } 'fistp' [lLqQsS]? { RET_INSN(5, fildstp, 0x070203, CPU_FPU); } 'fistpll' { RET_INSN_GAS(7, fbldstp, 0x07, CPU_FPU); } -- 2.40.0