From df143a6a12689ddf0c1aff094966ff4e0c12acf1 Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic <nemanja.i.ibm@gmail.com>
Date: Mon, 31 Oct 2016 19:02:54 +0000
Subject: [PATCH] NFC - Reorder test case names in a PPC test case

A few recent commits have messed up the order of some tests
in a PPC test case. This just reorders them in a sensible way.


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@285623 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/builtins-ppc-p9vector.c | 56 ++++++++++++++--------------
 1 file changed, 28 insertions(+), 28 deletions(-)

diff --git a/test/CodeGen/builtins-ppc-p9vector.c b/test/CodeGen/builtins-ppc-p9vector.c
index b41e88dbbc..1ae4412bf5 100644
--- a/test/CodeGen/builtins-ppc-p9vector.c
+++ b/test/CodeGen/builtins-ppc-p9vector.c
@@ -700,6 +700,34 @@ vector unsigned short test54(void) {
 // CHECK-NEXT: ret <8 x i16>
   return vec_popcnt (vusa);
 }
+vector double test55(void) {
+// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
+// CHECK-BE-NEXT: ret <2 x double>
+// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
+// CHECK-NEXT: ret <2 x double>
+  return vec_insert_exp (vda,vulb);
+}
+vector double test56(void) {
+// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
+// CHECK-BE-NEXT: ret <2 x double>
+// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
+// CHECK-NEXT: ret <2 x double>
+  return vec_insert_exp (vula, vulb);
+}
+vector float test57(void) {
+// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
+// CHECK-BE-NEXT: ret <4 x float>
+// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
+// CHECK-NEXT: ret <4 x float>
+  return vec_insert_exp (vfa,vuib);
+}
+vector float test58(void) {
+// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
+// CHECK-BE-NEXT: ret <4 x float>
+// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
+// CHECK-NEXT: ret <4 x float>
+  return vec_insert_exp (vuia,vuib);
+}
 signed int test59(void) {
 // CHECK-BE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>
 // CHECK-BE-NEXT: ret i32
@@ -775,31 +803,3 @@ vector unsigned __int128 test68(void) {
 // CHECK-NEXT: ret <1 x i128>
   return vec_parity_lsbb (vsi128a);
 }
-vector double test55(void) {
-// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
-// CHECK-BE-NEXT: ret <2 x double>
-// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
-// CHECK-NEXT: ret <2 x double>
-  return vec_insert_exp (vda,vulb);
-}
-vector double test56(void) {
-// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
-// CHECK-BE-NEXT: ret <2 x double>
-// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
-// CHECK-NEXT: ret <2 x double>
-  return vec_insert_exp (vula, vulb);
-}
-vector float test57(void) {
-// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
-// CHECK-BE-NEXT: ret <4 x float>
-// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
-// CHECK-NEXT: ret <4 x float>
-  return vec_insert_exp (vfa,vuib);
-}
-vector float test58(void) {
-// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
-// CHECK-BE-NEXT: ret <4 x float>
-// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
-// CHECK-NEXT: ret <4 x float>
-  return vec_insert_exp (vuia,vuib);
-}
-- 
2.40.0