From deeb131011b7e670ca8edd5cde3edd7ac053d99b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 9 May 2016 16:29:50 +0000 Subject: [PATCH] AMDGPU: Fold shift into cvt_f32_ubyteN git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268930 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIISelLowering.cpp | 16 ++++- test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 60 ++++++++++++++++- .../AMDGPU/llvm.AMDGPU.cvt_f32_ubyte.ll | 64 +++++++++++++++++++ 3 files changed, 137 insertions(+), 3 deletions(-) diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index 87d42f1552d..7436f95705a 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -2818,8 +2818,22 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N, case AMDGPUISD::CVT_F32_UBYTE2: case AMDGPUISD::CVT_F32_UBYTE3: { unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0; - SDValue Src = N->getOperand(0); + + if (Src.getOpcode() == ISD::SRL) { + // cvt_f32_ubyte0 (srl x, 16) -> cvt_f32_ubyte2 x + // cvt_f32_ubyte1 (srl x, 16) -> cvt_f32_ubyte3 x + // cvt_f32_ubyte0 (srl x, 8) -> cvt_f32_ubyte1 x + + if (const ConstantSDNode *C = dyn_cast(Src.getOperand(1))) { + unsigned SrcOffset = C->getZExtValue() + 8 * Offset; + if (SrcOffset < 32 && SrcOffset % 8 == 0) { + return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0 + SrcOffset / 8, DL, + MVT::f32, Src.getOperand(0)); + } + } + } + APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8); APInt KnownZero, KnownOne; diff --git a/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll index 67798864a0c..f85e4e9c598 100644 --- a/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll +++ b/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}load_i8_to_f32: @@ -170,9 +170,9 @@ define void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addr ret void } - ; We don't get these ones because of the zext, but instcombine removes ; them so it shouldn't really matter. +; SI-LABEL: {{^}}i8_zext_i32_to_f32: define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind { %load = load i8, i8 addrspace(1)* %in, align 1 %ext = zext i8 %load to i32 @@ -181,6 +181,7 @@ define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1 ret void } +; SI-LABEL: {{^}}v4i8_zext_v4i32_to_v4f32: define void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind { %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1 %ext = zext <4 x i8> %load to <4 x i32> @@ -188,3 +189,58 @@ define void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16 ret void } + +; SI-LABEL: {{^}}extract_byte0_to_f32: +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOT: [[VAL]] +; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[CONV]] +define void @extract_byte0_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { + %val = load i32, i32 addrspace(1)* %in + %and = and i32 %val, 255 + %cvt = uitofp i32 %and to float + store float %cvt, float addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}extract_byte1_to_f32: +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOT: [[VAL]] +; SI: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[CONV]] +define void @extract_byte1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { + %val = load i32, i32 addrspace(1)* %in + %srl = lshr i32 %val, 8 + %and = and i32 %srl, 255 + %cvt = uitofp i32 %and to float + store float %cvt, float addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}extract_byte2_to_f32: +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOT: [[VAL]] +; SI: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[CONV]] +define void @extract_byte2_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { + %val = load i32, i32 addrspace(1)* %in + %srl = lshr i32 %val, 16 + %and = and i32 %srl, 255 + %cvt = uitofp i32 %and to float + store float %cvt, float addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}extract_byte3_to_f32: +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOT: [[VAL]] +; SI: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[CONV]] +define void @extract_byte3_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { + %val = load i32, i32 addrspace(1)* %in + %srl = lshr i32 %val, 24 + %and = and i32 %srl, 255 + %cvt = uitofp i32 %and to float + store float %cvt, float addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.cvt_f32_ubyte.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.cvt_f32_ubyte.ll index 8b32f696449..612fe5bbe09 100644 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.cvt_f32_ubyte.ll +++ b/test/CodeGen/AMDGPU/llvm.AMDGPU.cvt_f32_ubyte.ll @@ -41,3 +41,67 @@ define void @test_unpack_byte3_to_float(float addrspace(1)* %out, i32 addrspace( store float %cvt, float addrspace(1)* %out, align 4 ret void } + +; SI-LABEL: {{^}}byte1_shift8: +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOT: [[VAL]] +; SI: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[CONV]] +define void @byte1_shift8(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { + %val = load i32, i32 addrspace(1)* %in, align 4 + %shift = lshr i32 %val, 8 + %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %shift) nounwind readnone + store float %cvt, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}byte1_shift7: +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI: v_lshrrev_b32_e32 [[SRL:v[0-9]+]], 7, [[VAL]] +; SI: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[SRL]] +; SI: buffer_store_dword [[CONV]] +define void @byte1_shift7(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { + %val = load i32, i32 addrspace(1)* %in, align 4 + %shift = lshr i32 %val, 7 + %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %shift) nounwind readnone + store float %cvt, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}byte1_shift16: +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOT: [[VAL]] +; SI: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[CONV]] +define void @byte1_shift16(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { + %val = load i32, i32 addrspace(1)* %in, align 4 + %shift = lshr i32 %val, 16 + %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %shift) nounwind readnone + store float %cvt, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}byte2_shift8: +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOT: [[VAL]] +; SI: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[CONV]] +define void @byte2_shift8(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { + %val = load i32, i32 addrspace(1)* %in, align 4 + %shift = lshr i32 %val, 8 + %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte2(i32 %shift) nounwind readnone + store float %cvt, float addrspace(1)* %out, align 4 + ret void +} + +; XXX - undef +; SI-LABEL: {{^}}byte1_shift24: +; SI: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], 0 +; SI: buffer_store_dword [[CONV]] +define void @byte1_shift24(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { + %val = load i32, i32 addrspace(1)* %in, align 4 + %shift = lshr i32 %val, 24 + %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %shift) nounwind readnone + store float %cvt, float addrspace(1)* %out, align 4 + ret void +} -- 2.50.1