From d966c4510d53f82b214164394c4598ea2295996d Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Sun, 9 Jun 2019 07:31:25 +0000 Subject: [PATCH] [AArch64][GlobalISel] Select immediate forms of cmp instructions. A simple re-use of the immediate operand matcher and renderer functions. rdar://43795178 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362896 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../AArch64/AArch64InstructionSelector.cpp | 22 ++++-- .../AArch64/GlobalISel/fold-fp-select.mir | 5 +- .../CodeGen/AArch64/GlobalISel/select-cmp.mir | 72 +++++++++++++++++++ 3 files changed, 91 insertions(+), 8 deletions(-) create mode 100644 test/CodeGen/AArch64/GlobalISel/select-cmp.mir diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp index df9fd739f57..cd3ca7cf37d 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -1858,6 +1858,11 @@ bool AArch64InstructionSelector::select(MachineInstr &I, return false; } + // Try to match immediate forms. + auto ImmFns = selectArithImmed(I.getOperand(3)); + if (ImmFns) + CmpOpc = CmpOpc == AArch64::SUBSWrr ? AArch64::SUBSWri : AArch64::SUBSXri; + // CSINC increments the result by one when the condition code is false. // Therefore, we have to invert the predicate to get an increment by 1 when // the predicate is true. @@ -1865,10 +1870,17 @@ bool AArch64InstructionSelector::select(MachineInstr &I, changeICMPPredToAArch64CC(CmpInst::getInversePredicate( (CmpInst::Predicate)I.getOperand(1).getPredicate())); - MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc)) - .addDef(ZReg) - .addUse(I.getOperand(2).getReg()) - .addUse(I.getOperand(3).getReg()); + auto CmpMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc)) + .addDef(ZReg) + .addUse(I.getOperand(2).getReg()); + + // If we matched a valid constant immediate, add those operands. + if (ImmFns) { + for (auto &RenderFn : *ImmFns) + RenderFn(CmpMI); + } else { + CmpMI.addUse(I.getOperand(3).getReg()); + } MachineInstr &CSetMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr)) @@ -1877,7 +1889,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I, .addUse(AArch64::WZR) .addImm(invCC); - constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI); constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI); I.eraseFromParent(); diff --git a/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir b/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir index 81aa2cfa146..1a2da0904a5 100644 --- a/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir +++ b/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir @@ -61,11 +61,10 @@ body: | ; CHECK-LABEL: name: using_icmp ; CHECK: liveins: $s0, $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0 - ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0 ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0 - ; CHECK: $wzr = SUBSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv + ; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[CSINCWr]] ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]] diff --git a/test/CodeGen/AArch64/GlobalISel/select-cmp.mir b/test/CodeGen/AArch64/GlobalISel/select-cmp.mir new file mode 100644 index 00000000000..456216d6a2d --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/select-cmp.mir @@ -0,0 +1,72 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s +--- +name: cmp_imm_32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $w0 + + ; CHECK-LABEL: name: cmp_imm_32 + ; CHECK: liveins: $w0 + ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 + ; CHECK: $wzr = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv + ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv + ; CHECK: $w0 = COPY [[CSINCWr]] + ; CHECK: RET_ReallyLR implicit $w0 + %0:gpr(s32) = COPY $w0 + %1:gpr(s32) = G_CONSTANT i32 42 + %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %1 + $w0 = COPY %5(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: cmp_imm_64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $x0 + + ; CHECK-LABEL: name: cmp_imm_64 + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: $xzr = SUBSXri [[COPY]], 42, 0, implicit-def $nzcv + ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv + ; CHECK: $w0 = COPY [[CSINCWr]] + ; CHECK: RET_ReallyLR implicit $w0 + %0:gpr(s64) = COPY $x0 + %1:gpr(s64) = G_CONSTANT i64 42 + %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1 + $w0 = COPY %5(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: cmp_imm_out_of_range +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1: + liveins: $x0 + + ; CHECK-LABEL: name: cmp_imm_out_of_range + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 13132 + ; CHECK: $xzr = SUBSXrr [[COPY]], [[MOVi64imm]], implicit-def $nzcv + ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv + ; CHECK: $w0 = COPY [[CSINCWr]] + ; CHECK: RET_ReallyLR implicit $w0 + %0:gpr(s64) = COPY $x0 + %1:gpr(s64) = G_CONSTANT i64 13132 + %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1 + $w0 = COPY %5(s32) + RET_ReallyLR implicit $w0 + +... -- 2.50.1