From d8ffcd8311a6b0914249f1bc8d6d796762a6b3c1 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 14 Jun 2016 15:16:35 +0000 Subject: [PATCH] Revert "AMDGPU/SI: Refactor fixup handling for constant addrspace variables" This reverts commit r272675. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272677 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 1 - lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 - lib/Target/AMDGPU/AMDGPUMCInstLower.cpp | 5 +-- .../AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp | 33 ++++++++++++++---- .../MCTargetDesc/AMDGPUELFObjectWriter.cpp | 18 ++++------ .../AMDGPU/MCTargetDesc/AMDGPUFixupKinds.h | 3 ++ .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h | 2 +- .../AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | 9 ++--- lib/Target/AMDGPU/SIISelLowering.cpp | 34 ------------------- lib/Target/AMDGPU/SIISelLowering.h | 3 +- lib/Target/AMDGPU/SIInstrInfo.cpp | 2 +- lib/Target/AMDGPU/SIInstrInfo.td | 6 +--- lib/Target/AMDGPU/SIInstructions.td | 6 ++-- 13 files changed, 50 insertions(+), 73 deletions(-) diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 37f6efa315f..7dc8fd5f518 100644 --- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -2779,7 +2779,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(CVT_F32_UBYTE3) NODE_NAME_CASE(BUILD_VERTICAL_VECTOR) NODE_NAME_CASE(CONST_DATA_PTR) - NODE_NAME_CASE(PC_ADD_REL_OFFSET) case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break; NODE_NAME_CASE(SENDMSG) NODE_NAME_CASE(INTERP_MOV) diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.h b/lib/Target/AMDGPU/AMDGPUISelLowering.h index ecf69f8779c..824732ad699 100644 --- a/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -297,7 +297,6 @@ enum NodeType : unsigned { INTERP_MOV, INTERP_P1, INTERP_P2, - PC_ADD_REL_OFFSET, FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE, STORE_MSKOR, LOAD_CONSTANT, diff --git a/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp index 0fd17b41f7e..51114b3ee44 100644 --- a/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp +++ b/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp @@ -70,10 +70,7 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { case MachineOperand::MO_GlobalAddress: { const GlobalValue *GV = MO.getGlobal(); MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(GV->getName())); - const MCExpr *SymExpr = MCSymbolRefExpr::create(Sym, Ctx); - const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr, - MCConstantExpr::create(MO.getOffset(), Ctx), Ctx); - MCOp = MCOperand::createExpr(Expr); + MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(Sym, Ctx)); break; } case MachineOperand::MO_ExternalSymbol: { diff --git a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp index 4dad1efbb30..1e66b3b0934 100644 --- a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -81,7 +81,6 @@ static unsigned getFixupKindNumBytes(unsigned Kind) { return 2; case FK_SecRel_4: case FK_Data_4: - case FK_PCRel_4: return 4; case FK_SecRel_8: case FK_Data_8: @@ -106,6 +105,27 @@ void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, break; } + case AMDGPU::fixup_si_rodata: { + uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset()); + // We emit constant data at the end of the text section and generate its + // address using the following code sequence: + // s_getpc_b64 s[0:1] + // s_add_u32 s0, s0, $symbol + // s_addc_u32 s1, s1, 0 + // + // s_getpc_b64 returns the address of the s_add_u32 instruction and then + // the fixup replaces $symbol with a literal constant, which is a + // pc-relative offset from the encoding of the $symbol operand to the + // constant data. + // + // What we want here is an offset from the start of the s_add_u32 + // instruction to the constant data, but since the encoding of $symbol + // starts 4 bytes after the start of the add instruction, we end up + // with an offset that is 4 bytes too small. This requires us to + // add 4 to the fixup value before applying it. + *Dst = Value + 4; + break; + } default: { // FIXME: Copied from AArch64 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); @@ -132,6 +152,7 @@ const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo( const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = { // name offset bits flags { "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_si_rodata", 0, 32, MCFixupKindInfo::FKF_IsPCRel } }; if (Kind < FirstTargetFixupKind) @@ -153,14 +174,14 @@ bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { namespace { class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend { - const Triple &TT; + bool Is64Bit; public: - ELFAMDGPUAsmBackend(const Target &T, const Triple &TT) : - AMDGPUAsmBackend(T), TT(TT) { } + ELFAMDGPUAsmBackend(const Target &T, bool Is64Bit) : + AMDGPUAsmBackend(T), Is64Bit(Is64Bit) { } MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { - return createAMDGPUELFObjectWriter(TT, OS); + return createAMDGPUELFObjectWriter(Is64Bit, OS); } }; @@ -170,5 +191,5 @@ MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { // Use 64-bit ELF for amdgcn - return new ELFAMDGPUAsmBackend(T, TT); + return new ELFAMDGPUAsmBackend(T, TT.getArch() == Triple::amdgcn); } diff --git a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp index a29ad5c7c7b..4302737396f 100644 --- a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp +++ b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp @@ -18,27 +18,23 @@ namespace { class AMDGPUELFObjectWriter : public MCELFObjectTargetWriter { public: - AMDGPUELFObjectWriter(const Triple &TT); + AMDGPUELFObjectWriter(bool Is64Bit); protected: unsigned getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const override { return Fixup.getKind(); } + }; } // End anonymous namespace -AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(const Triple &TT) - : MCELFObjectTargetWriter(TT.getArch() == Triple::amdgcn, // Is64Bit - ELF::ELFOSABI_AMDGPU_HSA, - ELF::EM_AMDGPU, - // HasRelocationAddend - TT.getOS() == Triple::AMDHSA) {} - +AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(bool Is64Bit) + : MCELFObjectTargetWriter(Is64Bit, ELF::ELFOSABI_AMDGPU_HSA, + ELF::EM_AMDGPU, false) { } -MCObjectWriter *llvm::createAMDGPUELFObjectWriter(const Triple &TT, - raw_pwrite_stream &OS) { - MCELFObjectTargetWriter *MOTW = new AMDGPUELFObjectWriter(TT); +MCObjectWriter *llvm::createAMDGPUELFObjectWriter(bool Is64Bit, raw_pwrite_stream &OS) { + MCELFObjectTargetWriter *MOTW = new AMDGPUELFObjectWriter(Is64Bit); return createELFObjectWriter(MOTW, OS, true); } diff --git a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUFixupKinds.h b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUFixupKinds.h index 20c1adfbc6b..a024f285cfa 100644 --- a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUFixupKinds.h +++ b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUFixupKinds.h @@ -18,6 +18,9 @@ enum Fixups { /// 16-bit PC relative fixup for SOPP branch instructions. fixup_si_sopp_br = FirstTargetFixupKind, + /// fixup for global addresses with constant initializers + fixup_si_rodata, + // Marker LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind diff --git a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h index 8a690291474..5f76860133c 100644 --- a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h +++ b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -46,7 +46,7 @@ MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII, MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); -MCObjectWriter *createAMDGPUELFObjectWriter(const Triple &TT, +MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit, raw_pwrite_stream &OS); } // End llvm namespace diff --git a/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp index 52787b64f7e..533a54c1a8b 100644 --- a/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -248,13 +248,14 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, return MRI.getEncodingValue(MO.getReg()); if (MO.isExpr()) { - const MCSymbolRefExpr *Expr = dyn_cast(MO.getExpr()); + const MCSymbolRefExpr *Expr = cast(MO.getExpr()); + const MCSymbol &Sym = Expr->getSymbol(); MCFixupKind Kind; - if (Expr && Expr->getSymbol().isExternal()) + if (Sym.isExternal()) Kind = FK_Data_4; else - Kind = FK_PCRel_4; - Fixups.push_back(MCFixup::create(4, MO.getExpr(), Kind, MI.getLoc())); + Kind = (MCFixupKind)AMDGPU::fixup_si_rodata; + Fixups.push_back(MCFixup::create(4, Expr, Kind, MI.getLoc())); } // Figure out the operand number, needed for isSrcOperand check diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index 3fd002696c9..a2b5722881e 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1416,40 +1416,6 @@ SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op, return DAG.getUNDEF(ASC->getValueType(0)); } -SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI, - SDValue Op, - SelectionDAG &DAG) const { - GlobalAddressSDNode *GSD = cast(Op); - - if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS) - return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); - - SDLoc DL(GSD); - const GlobalValue *GV = GSD->getGlobal(); - MVT PtrVT = getPointerTy(DAG.getDataLayout(), GSD->getAddressSpace()); - - // In order to support pc-relative addressing, the PC_ADD_REL_OFFSET SDNode is - // lowered to the following code sequence: - // s_getpc_b64 s[0:1] - // s_add_u32 s0, s0, $symbol - // s_addc_u32 s1, s1, 0 - // - // s_getpc_b64 returns the address of the s_add_u32 instruction and then - // a fixup or relocation is emitted to replace $symbol with a literal - // constant, which is a pc-relative offset from the encoding of the $symbol - // operand to the global variable. - // - // What we want here is an offset from the value returned by s_getpc - // (which is the address of the s_add_u32 instruction) to the global - // variable, but since the encoding of $symbol starts 4 bytes after the start - // of the s_add_u32 instruction, we end up with an offset that is 4 bytes too - // small. This requires us to add 4 to the global variable offset in order to - // compute the correct address. - SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, - GSD->getOffset() + 4); - return DAG.getNode(AMDGPUISD::PC_ADD_REL_OFFSET, DL, PtrVT, GA); -} - SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const { // We can't use S_MOV_B32 directly, because there is no way to specify m0 as diff --git a/lib/Target/AMDGPU/SIISelLowering.h b/lib/Target/AMDGPU/SIISelLowering.h index 20e30c079dc..bc85a0e6a37 100644 --- a/lib/Target/AMDGPU/SIISelLowering.h +++ b/lib/Target/AMDGPU/SIISelLowering.h @@ -23,8 +23,7 @@ namespace llvm { class SITargetLowering final : public AMDGPUTargetLowering { SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &DL, SDValue Chain, unsigned Offset, bool Signed) const; - SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, - SelectionDAG &DAG) const override; + SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, MVT VT, unsigned Offset) const; diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp index b33f07e6f22..af246c07bf7 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -914,7 +914,7 @@ bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { break; } - case AMDGPU::SI_PC_ADD_REL_OFFSET: { + case AMDGPU::SI_CONSTDATA_PTR: { const SIRegisterInfo *TRI = static_cast(ST.getRegisterInfo()); MachineFunction &MF = *MBB.getParent(); diff --git a/lib/Target/AMDGPU/SIInstrInfo.td b/lib/Target/AMDGPU/SIInstrInfo.td index f0040ce3866..b2ed155f6c9 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.td +++ b/lib/Target/AMDGPU/SIInstrInfo.td @@ -137,10 +137,6 @@ def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">; def SIsampled : SDSample<"AMDGPUISD::SAMPLED">; def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">; -def SIpc_add_rel_offset : SDNode<"AMDGPUISD::PC_ADD_REL_OFFSET", - SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisSameAs<0,1>]> ->; - //===----------------------------------------------------------------------===// // PatFrags for FLAT instructions //===----------------------------------------------------------------------===// @@ -458,7 +454,7 @@ def sopp_brtarget : Operand { let ParserMatchClass = SoppBrTarget; } -def si_ga : Operand; +def const_ga : Operand; def InterpSlot : Operand { let PrintMethod = "printInterpSlot"; diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td index bc300b74d34..61aa65c1caa 100644 --- a/lib/Target/AMDGPU/SIInstructions.td +++ b/lib/Target/AMDGPU/SIInstructions.td @@ -2107,10 +2107,10 @@ defm SI_SPILL_V512 : SI_SPILL_VGPR ; let Defs = [SCC] in { -def SI_PC_ADD_REL_OFFSET : InstSI < +def SI_CONSTDATA_PTR : InstSI < (outs SReg_64:$dst), - (ins si_ga:$ptr), - "", [(set SReg_64:$dst, (i64 (SIpc_add_rel_offset (tglobaladdr:$ptr))))] + (ins const_ga:$ptr), + "", [(set SReg_64:$dst, (i64 (AMDGPUconstdata_ptr (tglobaladdr:$ptr))))] > { let SALU = 1; } -- 2.50.1