From d8ebe2971a8a9bcd9d0fd42771c738e7698116e6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Mon, 25 Mar 2019 21:10:12 +0000
Subject: [PATCH] AMDGPU: Set hasSideEffects 0 on _term instructions

These were defaulting to true, but they are just wrappers around bit
operations. This avoids regressions in the exec mask optimization
passes in a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356952 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/AMDGPU/SIInstructions.td | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td
index 869deb93679..b0ab7032d97 100644
--- a/lib/Target/AMDGPU/SIInstructions.td
+++ b/lib/Target/AMDGPU/SIInstructions.td
@@ -172,12 +172,14 @@ def S_MOV_B64_term : SPseudoInstSI<(outs SReg_64:$dst),
    (ins SSrc_b64:$src0)> {
   let isAsCheapAsAMove = 1;
   let isTerminator = 1;
+  let hasSideEffects = 0;
 }
 
 def S_XOR_B64_term : SPseudoInstSI<(outs SReg_64:$dst),
    (ins SSrc_b64:$src0, SSrc_b64:$src1)> {
   let isAsCheapAsAMove = 1;
   let isTerminator = 1;
+  let hasSideEffects = 0;
   let Defs = [SCC];
 }
 
@@ -185,6 +187,7 @@ def S_ANDN2_B64_term : SPseudoInstSI<(outs SReg_64:$dst),
    (ins SSrc_b64:$src0, SSrc_b64:$src1)> {
   let isAsCheapAsAMove = 1;
   let isTerminator = 1;
+  let hasSideEffects = 0;
 }
 
 def WAVE_BARRIER : SPseudoInstSI<(outs), (ins),
-- 
2.50.1