From d4fc66ef142a445fff985707c5bb9b853e8a6021 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Tue, 28 Mar 2017 23:03:19 +0000 Subject: [PATCH] Default enable the rtm feature only on skylake and later for now because Intel disabled the feature on some haswell and broadwell processors: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf the -mrtm option will still work normally. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@298956 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Basic/Targets.cpp | 2 +- test/Preprocessor/predefined-arch-macros.c | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp index 23ef9f8dd6..d80a8d5efe 100644 --- a/lib/Basic/Targets.cpp +++ b/lib/Basic/Targets.cpp @@ -3194,6 +3194,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "mpx", true); setFeatureEnabledImpl(Features, "sgx", true); setFeatureEnabledImpl(Features, "clflushopt", true); + setFeatureEnabledImpl(Features, "rtm", true); LLVM_FALLTHROUGH; case CK_Broadwell: setFeatureEnabledImpl(Features, "rdseed", true); @@ -3204,7 +3205,6 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "bmi2", true); - setFeatureEnabledImpl(Features, "rtm", true); setFeatureEnabledImpl(Features, "fma", true); setFeatureEnabledImpl(Features, "movbe", true); LLVM_FALLTHROUGH; diff --git a/test/Preprocessor/predefined-arch-macros.c b/test/Preprocessor/predefined-arch-macros.c index b63b6ddff5..5252d2ce0d 100644 --- a/test/Preprocessor/predefined-arch-macros.c +++ b/test/Preprocessor/predefined-arch-macros.c @@ -525,7 +525,6 @@ // CHECK_CORE_AVX2_M32: #define __PCLMUL__ 1 // CHECK_CORE_AVX2_M32: #define __POPCNT__ 1 // CHECK_CORE_AVX2_M32: #define __RDRND__ 1 -// CHECK_CORE_AVX2_M32: #define __RTM__ 1 // CHECK_CORE_AVX2_M32: #define __SSE2__ 1 // CHECK_CORE_AVX2_M32: #define __SSE3__ 1 // CHECK_CORE_AVX2_M32: #define __SSE4_1__ 1 @@ -555,7 +554,6 @@ // CHECK_CORE_AVX2_M64: #define __PCLMUL__ 1 // CHECK_CORE_AVX2_M64: #define __POPCNT__ 1 // CHECK_CORE_AVX2_M64: #define __RDRND__ 1 -// CHECK_CORE_AVX2_M64: #define __RTM__ 1 // CHECK_CORE_AVX2_M64: #define __SSE2_MATH__ 1 // CHECK_CORE_AVX2_M64: #define __SSE2__ 1 // CHECK_CORE_AVX2_M64: #define __SSE3__ 1 @@ -591,7 +589,6 @@ // CHECK_BROADWELL_M32: #define __POPCNT__ 1 // CHECK_BROADWELL_M32: #define __RDRND__ 1 // CHECK_BROADWELL_M32: #define __RDSEED__ 1 -// CHECK_BROADWELL_M32: #define __RTM__ 1 // CHECK_BROADWELL_M32: #define __SSE2__ 1 // CHECK_BROADWELL_M32: #define __SSE3__ 1 // CHECK_BROADWELL_M32: #define __SSE4_1__ 1 @@ -623,7 +620,6 @@ // CHECK_BROADWELL_M64: #define __POPCNT__ 1 // CHECK_BROADWELL_M64: #define __RDRND__ 1 // CHECK_BROADWELL_M64: #define __RDSEED__ 1 -// CHECK_BROADWELL_M64: #define __RTM__ 1 // CHECK_BROADWELL_M64: #define __SSE2_MATH__ 1 // CHECK_BROADWELL_M64: #define __SSE2__ 1 // CHECK_BROADWELL_M64: #define __SSE3__ 1 -- 2.40.0