From d42372792dacc54929fa8cfcefdf1a47b556417a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 27 Jun 2019 05:52:00 +0000 Subject: [PATCH] [X86] Remove (vzext_movl (scalar_to_vector (load))) matching code from selectScalarSSELoad. I think this will be turning into vzext_load during DAG combine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364499 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelDAGToDAG.cpp | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 544a3fa922d..2a4477be43c 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -2321,23 +2321,6 @@ bool X86DAGToDAGISel::selectScalarSSELoad(SDNode *Root, SDNode *Parent, } } - // Also handle the case where we explicitly require zeros in the top - // elements. This is a vector shuffle from the zero vector. - if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() && - // Check to see if the top elements are all zeros (or bitcast of zeros). - N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && - N.getOperand(0).getNode()->hasOneUse()) { - PatternNodeWithChain = N.getOperand(0).getOperand(0); - if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) && - IsProfitableToFold(PatternNodeWithChain, N.getNode(), Root) && - IsLegalToFold(PatternNodeWithChain, N.getNode(), Root, OptLevel)) { - // Okay, this is a zero extending load. Fold it. - LoadSDNode *LD = cast(PatternNodeWithChain); - return selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, - Segment); - } - } - return false; } -- 2.50.1