From d081dde5cf232254676c68362846fd3e6b76a669 Mon Sep 17 00:00:00 2001 From: Andrea Di Biagio Date: Thu, 6 Nov 2014 12:08:57 +0000 Subject: [PATCH] [X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@221449 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Basic/Targets.cpp | 19 +++++++------------ test/Preprocessor/predefined-arch-macros.c | 10 ++++++++++ 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp index d41105fef6..653f689a5b 100644 --- a/lib/Basic/Targets.cpp +++ b/lib/Basic/Targets.cpp @@ -2276,14 +2276,6 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap &Features) const { setFeatureEnabledImpl(Features, "prfchw", true); setFeatureEnabledImpl(Features, "cx16", true); break; - case CK_BDVER1: - setFeatureEnabledImpl(Features, "xop", true); - setFeatureEnabledImpl(Features, "lzcnt", true); - setFeatureEnabledImpl(Features, "aes", true); - setFeatureEnabledImpl(Features, "pclmul", true); - setFeatureEnabledImpl(Features, "prfchw", true); - setFeatureEnabledImpl(Features, "cx16", true); - break; case CK_BDVER4: setFeatureEnabledImpl(Features, "avx2", true); setFeatureEnabledImpl(Features, "bmi2", true); @@ -2292,15 +2284,18 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap &Features) const { setFeatureEnabledImpl(Features, "fsgsbase", true); // FALLTHROUGH case CK_BDVER2: + setFeatureEnabledImpl(Features, "bmi", true); + setFeatureEnabledImpl(Features, "fma", true); + setFeatureEnabledImpl(Features, "f16c", true); + setFeatureEnabledImpl(Features, "tbm", true); + // FALLTHROUGH + case CK_BDVER1: + // xop implies avx, sse4a and fma4. setFeatureEnabledImpl(Features, "xop", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "pclmul", true); setFeatureEnabledImpl(Features, "prfchw", true); - setFeatureEnabledImpl(Features, "bmi", true); - setFeatureEnabledImpl(Features, "fma", true); - setFeatureEnabledImpl(Features, "f16c", true); - setFeatureEnabledImpl(Features, "tbm", true); setFeatureEnabledImpl(Features, "cx16", true); break; } diff --git a/test/Preprocessor/predefined-arch-macros.c b/test/Preprocessor/predefined-arch-macros.c index 8b58c9ce01..5bdbdbc622 100644 --- a/test/Preprocessor/predefined-arch-macros.c +++ b/test/Preprocessor/predefined-arch-macros.c @@ -1342,8 +1342,11 @@ // CHECK_BTVER2_M32-NOT: #define __3dNOW__ 1 // CHECK_BTVER2_M32: #define __AES__ 1 // CHECK_BTVER2_M32: #define __AVX__ 1 +// CHECK_BTVER2_M32: #define __BMI__ 1 +// CHECK_BTVER2_M32: #define __F16C__ 1 // CHECK_BTVER2_M32: #define __LZCNT__ 1 // CHECK_BTVER2_M32: #define __MMX__ 1 +// CHECK_BTVER2_M32: #define __PCLMUL__ 1 // CHECK_BTVER2_M32: #define __POPCNT__ 1 // CHECK_BTVER2_M32: #define __PRFCHW__ 1 // CHECK_BTVER2_M32: #define __SSE2_MATH__ 1 @@ -1365,8 +1368,11 @@ // CHECK_BTVER2_M64-NOT: #define __3dNOW__ 1 // CHECK_BTVER2_M64: #define __AES__ 1 // CHECK_BTVER2_M64: #define __AVX__ 1 +// CHECK_BTVER2_M64: #define __BMI__ 1 +// CHECK_BTVER2_M64: #define __F16C__ 1 // CHECK_BTVER2_M64: #define __LZCNT__ 1 // CHECK_BTVER2_M64: #define __MMX__ 1 +// CHECK_BTVER2_M64: #define __PCLMUL__ 1 // CHECK_BTVER2_M64: #define __POPCNT__ 1 // CHECK_BTVER2_M64: #define __PRFCHW__ 1 // CHECK_BTVER2_M64: #define __SSE2_MATH__ 1 @@ -1518,6 +1524,7 @@ // CHECK_BDVER3_M32: #define __F16C__ 1 // CHECK_BDVER3_M32: #define __FMA4__ 1 // CHECK_BDVER3_M32: #define __FMA__ 1 +// CHECK_BDVER3_M32: #define __FSGSBASE__ 1 // CHECK_BDVER3_M32: #define __LZCNT__ 1 // CHECK_BDVER3_M32: #define __MMX__ 1 // CHECK_BDVER3_M32: #define __PCLMUL__ 1 @@ -1550,6 +1557,7 @@ // CHECK_BDVER3_M64: #define __F16C__ 1 // CHECK_BDVER3_M64: #define __FMA4__ 1 // CHECK_BDVER3_M64: #define __FMA__ 1 +// CHECK_BDVER3_M64: #define __FSGSBASE__ 1 // CHECK_BDVER3_M64: #define __LZCNT__ 1 // CHECK_BDVER3_M64: #define __MMX__ 1 // CHECK_BDVER3_M64: #define __PCLMUL__ 1 @@ -1586,6 +1594,7 @@ // CHECK_BDVER4_M32: #define __F16C__ 1 // CHECK_BDVER4_M32: #define __FMA4__ 1 // CHECK_BDVER4_M32: #define __FMA__ 1 +// CHECK_BDVER4_M32: #define __FSGSBASE__ 1 // CHECK_BDVER4_M32: #define __LZCNT__ 1 // CHECK_BDVER4_M32: #define __MMX__ 1 // CHECK_BDVER4_M32: #define __PCLMUL__ 1 @@ -1620,6 +1629,7 @@ // CHECK_BDVER4_M64: #define __F16C__ 1 // CHECK_BDVER4_M64: #define __FMA4__ 1 // CHECK_BDVER4_M64: #define __FMA__ 1 +// CHECK_BDVER4_M64: #define __FSGSBASE__ 1 // CHECK_BDVER4_M64: #define __LZCNT__ 1 // CHECK_BDVER4_M64: #define __MMX__ 1 // CHECK_BDVER4_M64: #define __PCLMUL__ 1 -- 2.40.0