From cecf102e0cb2fa8a21f2817c42ad53f25acc0997 Mon Sep 17 00:00:00 2001 From: Konstantin Zhuravlyov Date: Tue, 17 Oct 2017 20:03:21 +0000 Subject: [PATCH] AMDGPU: Start generating metadata for MaxFlatWorkGroupSize Differential Revision: https://reviews.llvm.org/D38958 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316024 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 2 +- .../attr-amdgpu-flat-work-group-size.ll | 15 ++++++++++++- .../AMDGPU/hsa-metadata-kernel-code-props.ll | 21 ++++++++++--------- .../AMDGPU/hsa-metadata-kernel-code-props.s | 2 ++ 4 files changed, 28 insertions(+), 12 deletions(-) diff --git a/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 1adede07ed1..52ac53260b0 100644 --- a/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -1179,7 +1179,7 @@ AMDGPU::HSAMD::Kernel::CodeProps::Metadata AMDGPUAsmPrinter::getHSACodeProps( HSACodeProps.mWavefrontSize = STM.getWavefrontSize(); HSACodeProps.mNumSGPRs = CurrentProgramInfo.NumSGPR; HSACodeProps.mNumVGPRs = CurrentProgramInfo.NumVGPR; - // TODO: Emit HSACodeProps.mMaxFlatWorkgroupSize. + HSACodeProps.mMaxFlatWorkgroupSize = MFI.getMaxFlatWorkGroupSize(); HSACodeProps.mIsDynamicCallStack = ProgramInfo.DynamicCallStack; HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled(); diff --git a/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll b/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll index a0694fb1e3c..3e2a5d2e4cc 100644 --- a/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll +++ b/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefix=CHECK %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=HSAMD %s ; CHECK-LABEL: {{^}}min_64_max_64: ; CHECK: SGPRBlocks: 0 @@ -127,3 +128,15 @@ define amdgpu_kernel void @min_1024_max_2048() #3 { ret void } attributes #3 = {"amdgpu-flat-work-group-size"="1024,2048"} + +; HSAMD: NT_AMD_AMDGPU_HSA_METADATA (HSA Metadata) +; HSAMD: Version: [ 1, 0 ] +; HSAMD: Kernels: +; HSAMD: - Name: min_64_max_64 +; HSAMD: MaxFlatWorkgroupSize: 64 +; HSAMD: - Name: min_64_max_128 +; HSAMD: MaxFlatWorkgroupSize: 128 +; HSAMD: - Name: min_128_max_128 +; HSAMD: MaxFlatWorkgroupSize: 128 +; HSAMD: - Name: min_1024_max_2048 +; HSAMD: MaxFlatWorkgroupSize: 2048 diff --git a/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll b/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll index ae839bb079a..177dbd78a5f 100644 --- a/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll +++ b/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll @@ -9,17 +9,18 @@ ; CHECK: - Name: test ; CHECK: SymbolName: 'test@kd' ; CHECK: CodeProps: -; CHECK: KernargSegmentSize: 24 -; CHECK: GroupSegmentFixedSize: 0 +; CHECK: KernargSegmentSize: 24 +; CHECK: GroupSegmentFixedSize: 0 ; CHECK: PrivateSegmentFixedSize: 0 -; CHECK: KernargSegmentAlign: 8 -; CHECK: WavefrontSize: 64 -; GFX700: NumSGPRs: 6 -; GFX800: NumSGPRs: 96 -; GFX900: NumSGPRs: 6 -; GFX700: NumVGPRs: 4 -; GFX800: NumVGPRs: 6 -; GFX900: NumVGPRs: 6 +; CHECK: KernargSegmentAlign: 8 +; CHECK: WavefrontSize: 64 +; GFX700: NumSGPRs: 6 +; GFX800: NumSGPRs: 96 +; GFX900: NumSGPRs: 6 +; GFX700: NumVGPRs: 4 +; GFX800: NumVGPRs: 6 +; GFX900: NumVGPRs: 6 +; CHECK: MaxFlatWorkgroupSize: 256 define amdgpu_kernel void @test( half addrspace(1)* %r, half addrspace(1)* %a, diff --git a/test/MC/AMDGPU/hsa-metadata-kernel-code-props.s b/test/MC/AMDGPU/hsa-metadata-kernel-code-props.s index e290235b16c..d56fcfcf064 100644 --- a/test/MC/AMDGPU/hsa-metadata-kernel-code-props.s +++ b/test/MC/AMDGPU/hsa-metadata-kernel-code-props.s @@ -13,6 +13,7 @@ // CHECK: PrivateSegmentFixedSize: 16 // CHECK: KernargSegmentAlign: 16 // CHECK: WavefrontSize: 64 +// CHECK: MaxFlatWorkgroupSize: 256 .amd_amdgpu_hsa_metadata Version: [ 1, 0 ] Printf: [ '1:1:4:%d\n', '2:1:8:%g\n' ] @@ -25,4 +26,5 @@ PrivateSegmentFixedSize: 16 KernargSegmentAlign: 16 WavefrontSize: 64 + MaxFlatWorkgroupSize: 256 .end_amd_amdgpu_hsa_metadata -- 2.40.0