From cb22b0f62e8f436cabb5daf6d86f5d186cc424dc Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 15 Feb 2019 19:21:39 +0000 Subject: [PATCH] [X86] Move all the SSE legality checks out of FP_TO_INTHelper and up to LowerFP_TO_INT. NFCI These checks aren't needed on the call to FP_TO_INTHelper from the type legalizer for splitting i64. We always want to use X87 FIST/FISTT to memory there. Moving up the SSE checks will allow this routine to focus on what it cares about and makes its return semantics cleaner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354161 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 36 ++++++++++++------------------ 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 2fa50635a6a..47c608dbabd 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -18066,13 +18066,10 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation // is legal, or has an fp128 or f16 source (which needs to be promoted to f32), -// just return an pair. +// just return an SDValue(). // Otherwise it is assumed to be a conversion from one of f32, f64 or f80 -// to i16, i32 or i64, and we lower it to a legal sequence. -// If lowered to the final integer result we return a pair. -// Otherwise we lower it to a sequence ending with a FIST, return a -// pair, and the caller is responsible for loading -// the final integer result from StackSlot. +// to i16, i32 or i64, and we lower it to a legal sequence and return the +// result. SDValue X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { @@ -18091,14 +18088,9 @@ X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, // If using FIST to compute an unsigned i64, we'll need some fixup // to handle values above the maximum signed i64. A FIST is always // used for the 32-bit subtarget, but also for f80 on a 64-bit target. - bool UnsignedFixup = !IsSigned && - DstTy == MVT::i64 && - (!Subtarget.is64Bit() || - !isScalarFPTypeInSSEReg(TheVT)); + bool UnsignedFixup = !IsSigned && DstTy == MVT::i64; if (!IsSigned && DstTy != MVT::i64) { - assert(!Subtarget.hasAVX512() && - "AVX512 should have already been handled!"); // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST. // The low 32 bits of the fist result will have the correct uint32 result. assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); @@ -18109,12 +18101,6 @@ X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, DstTy.getSimpleVT() >= MVT::i16 && "Unknown FP_TO_INT to lower!"); - // These are really Legal. - if (DstTy == MVT::i32 && isScalarFPTypeInSSEReg(TheVT)) - return SDValue(); - if (Subtarget.is64Bit() && DstTy == MVT::i64 && isScalarFPTypeInSSEReg(TheVT)) - return SDValue(); - // We lower FP->int64 into FISTP64 followed by a load from a temporary // stack slot. MachineFunction &MF = DAG.getMachineFunction(); @@ -18737,9 +18723,11 @@ SDValue X86TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const { assert(!VT.isVector()); + bool UseSSEReg = isScalarFPTypeInSSEReg(SrcVT); + if (!IsSigned && Subtarget.hasAVX512()) { // Conversions from f32/f64 should be legal. - if (SrcVT != MVT::f80) + if (UseSSEReg) return Op; // Use default expansion. @@ -18748,17 +18736,21 @@ SDValue X86TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const { } // Promote i16 to i32 if we can use a SSE operation. - if (VT == MVT::i16 && isScalarFPTypeInSSEReg(SrcVT)) { + if (VT == MVT::i16 && UseSSEReg) { assert(IsSigned && "Expected i16 FP_TO_UINT to have been promoted!"); SDValue Res = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Src); return DAG.getNode(ISD::TRUNCATE, dl, VT, Res); } + // If this is a SINT_TO_FP using SSEReg we're done. + if (UseSSEReg && IsSigned) + return Op; + + // Fall back to X87. if (SDValue V = FP_TO_INTHelper(Op, DAG, IsSigned)) return V; - // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. - return Op; + llvm_unreachable("Expected FP_TO_INTHelper to handle all remaining cases."); } static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) { -- 2.40.0