From c628c1e0b40b7eca79a4f2d3a9d4befbc171eeb8 Mon Sep 17 00:00:00 2001
From: Michael Kuperstein <michael.m.kuperstein@intel.com>
Date: Wed, 4 Nov 2015 11:17:53 +0000
Subject: [PATCH] [X86] DAGCombine should not introduce FILD in soft-float mode
The x86 "sitofp i64 to double" dag combine, in 32-bit mode, lowers sitofp
directly to X86ISD::FILD (or FILD_FLAG). This should not be done in soft-float mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252042 91177308-0d34-0410-b5e6-96231b3b80d8
---
lib/Target/X86/X86ISelLowering.cpp | 4 ++--
test/CodeGen/X86/soft-sitofp.ll | 15 +++++++++++++++
2 files changed, 17 insertions(+), 2 deletions(-)
create mode 100644 test/CodeGen/X86/soft-sitofp.ll
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 4240aaafe57..3434f8c7f0b 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -26419,8 +26419,8 @@ static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
}
// Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
- // a 32-bit target where SSE doesn't support i64->FP operations.
- if (Op0.getOpcode() == ISD::LOAD) {
+ // a 32-bit target where SSE doesn't support i64->FP operations.
+ if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
EVT LdVT = Ld->getValueType(0);
diff --git a/test/CodeGen/X86/soft-sitofp.ll b/test/CodeGen/X86/soft-sitofp.ll
new file mode 100644
index 00000000000..da26c7f7641
--- /dev/null
+++ b/test/CodeGen/X86/soft-sitofp.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+target triple = "i386-pc-linux"
+
+; Function Attrs: nounwind
+; CHECK-LABEL: ll_to_d:
+; CHECK: calll __floatdidf
+define double @ll_to_d(i64 %n) #0 {
+entry:
+ %conv = sitofp i64 %n to double
+ ret double %conv
+}
+
+attributes #0 = { nounwind "use-soft-float"="true" }
--
2.40.0