From c46faf029e8e9c4c8fc4b31cd5207aec80baf4c0 Mon Sep 17 00:00:00 2001 From: Geoff Berry Date: Mon, 19 Jun 2017 21:57:44 +0000 Subject: [PATCH] [AArch64][Falkor] Fix MOVZ sched predicate to not assert on non-imm operands (e.g. blockaddress). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305752 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64SchedFalkorDetails.td | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/Target/AArch64/AArch64SchedFalkorDetails.td b/lib/Target/AArch64/AArch64SchedFalkorDetails.td index 5e5e089f963..6081fbdcb0b 100644 --- a/lib/Target/AArch64/AArch64SchedFalkorDetails.td +++ b/lib/Target/AArch64/AArch64SchedFalkorDetails.td @@ -519,7 +519,8 @@ def FalkorReadIncSt : SchedReadAdvance<1, [FalkorWr_LdStInc_none_3cyc]>; // SchedPredicates and WriteVariants for Immediate Zero and LSLFast/ASRFast // ----------------------------------------------------------------------------- -def FalkorImmZPred : SchedPredicate<[{MI->getOperand(1).getImm() == 0}]>; +def FalkorImmZPred : SchedPredicate<[{MI->getOperand(1).isImm() && + MI->getOperand(1).getImm() == 0}]>; def FalkorOp1ZrReg : SchedPredicate<[{MI->getOperand(1).getReg() == AArch64::WZR || MI->getOperand(1).getReg() == AArch64::XZR}]>; -- 2.40.0