From c39fbcaf44e5a6de668cd75fbc8d903b3b9a12a5 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 21 Feb 2017 08:05:59 +0000 Subject: [PATCH] [X86] Remove sse3 intrinsic tests from the avx intrinsics test file. They are all covered by the SSE3 intrinsics test with SSE2, AVX, and AVX512 command lines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295705 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/avx-intrinsics-x86.ll | 114 +----------------------- test/CodeGen/X86/sse3-intrinsics-x86.ll | 34 ++++++- 2 files changed, 35 insertions(+), 113 deletions(-) diff --git a/test/CodeGen/X86/avx-intrinsics-x86.ll b/test/CodeGen/X86/avx-intrinsics-x86.ll index 019256efccd..bb8d6450b78 100644 --- a/test/CodeGen/X86/avx-intrinsics-x86.ll +++ b/test/CodeGen/X86/avx-intrinsics-x86.ll @@ -2,84 +2,6 @@ ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=avx,aes,pclmul -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX ; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=skx -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL -define <2 x double> @test_x86_sse3_addsub_pd(<2 x double> %a0, <2 x double> %a1) { -; CHECK-LABEL: test_x86_sse3_addsub_pd: -; CHECK: ## BB#0: -; CHECK-NEXT: vaddsubpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd0,0xc1] -; CHECK-NEXT: retl ## encoding: [0xc3] - %res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone - - -define <4 x float> @test_x86_sse3_addsub_ps(<4 x float> %a0, <4 x float> %a1) { -; CHECK-LABEL: test_x86_sse3_addsub_ps: -; CHECK: ## BB#0: -; CHECK-NEXT: vaddsubps %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0xd0,0xc1] -; CHECK-NEXT: retl ## encoding: [0xc3] - %res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone - - -define <2 x double> @test_x86_sse3_hadd_pd(<2 x double> %a0, <2 x double> %a1) { -; CHECK-LABEL: test_x86_sse3_hadd_pd: -; CHECK: ## BB#0: -; CHECK-NEXT: vhaddpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x7c,0xc1] -; CHECK-NEXT: retl ## encoding: [0xc3] - %res = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>) nounwind readnone - - -define <4 x float> @test_x86_sse3_hadd_ps(<4 x float> %a0, <4 x float> %a1) { -; CHECK-LABEL: test_x86_sse3_hadd_ps: -; CHECK: ## BB#0: -; CHECK-NEXT: vhaddps %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x7c,0xc1] -; CHECK-NEXT: retl ## encoding: [0xc3] - %res = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone - - -define <2 x double> @test_x86_sse3_hsub_pd(<2 x double> %a0, <2 x double> %a1) { -; CHECK-LABEL: test_x86_sse3_hsub_pd: -; CHECK: ## BB#0: -; CHECK-NEXT: vhsubpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x7d,0xc1] -; CHECK-NEXT: retl ## encoding: [0xc3] - %res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone - - -define <4 x float> @test_x86_sse3_hsub_ps(<4 x float> %a0, <4 x float> %a1) { -; CHECK-LABEL: test_x86_sse3_hsub_ps: -; CHECK: ## BB#0: -; CHECK-NEXT: vhsubps %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x7d,0xc1] -; CHECK-NEXT: retl ## encoding: [0xc3] - %res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone - - -define <16 x i8> @test_x86_sse3_ldu_dq(i8* %a0) { -; CHECK-LABEL: test_x86_sse3_ldu_dq: -; CHECK: ## BB#0: -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04] -; CHECK-NEXT: vlddqu (%eax), %xmm0 ## encoding: [0xc5,0xfb,0xf0,0x00] -; CHECK-NEXT: retl ## encoding: [0xc3] - %res = call <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %a0) ; <<16 x i8>> [#uses=1] - ret <16 x i8> %res -} -declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8*) nounwind readonly - - define <2 x double> @test_x86_sse41_blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) { ; CHECK-LABEL: test_x86_sse41_blendvpd: ; CHECK: ## BB#0: @@ -1923,34 +1845,6 @@ define void @test_x86_avx_vzeroupper() { } declare void @llvm.x86.avx.vzeroupper() nounwind -; Make sure instructions with no AVX equivalents, but are associated with SSEX feature flags still work - -define void @monitor(i8* %P, i32 %E, i32 %H) nounwind { -; CHECK-LABEL: monitor: -; CHECK: ## BB#0: -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx ## encoding: [0x8b,0x54,0x24,0x0c] -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x08] -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04] -; CHECK-NEXT: leal (%eax), %eax ## encoding: [0x8d,0x00] -; CHECK-NEXT: monitor ## encoding: [0x0f,0x01,0xc8] -; CHECK-NEXT: retl ## encoding: [0xc3] - tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H) - ret void -} -declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind - -define void @mwait(i32 %E, i32 %H) nounwind { -; CHECK-LABEL: mwait: -; CHECK: ## BB#0: -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04] -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08] -; CHECK-NEXT: mwait ## encoding: [0x0f,0x01,0xc9] -; CHECK-NEXT: retl ## encoding: [0xc3] - tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H) - ret void -} -declare void @llvm.x86.sse3.mwait(i32, i32) nounwind - define i32 @crc32_32_8(i32 %a, i8 %b) nounwind { ; CHECK-LABEL: crc32_32_8: ; CHECK: ## BB#0: @@ -1988,8 +1882,8 @@ define void @movnt_dq(i8* %p, <2 x i64> %a1) nounwind { ; AVX-LABEL: movnt_dq: ; AVX: ## BB#0: ; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04] -; AVX-NEXT: vpaddq LCPI136_0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd4,0x05,A,A,A,A] -; AVX-NEXT: ## fixup A - offset: 4, value: LCPI136_0, kind: FK_Data_4 +; AVX-NEXT: vpaddq LCPI127_0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd4,0x05,A,A,A,A] +; AVX-NEXT: ## fixup A - offset: 4, value: LCPI127_0, kind: FK_Data_4 ; AVX-NEXT: vmovntdq %ymm0, (%eax) ## encoding: [0xc5,0xfd,0xe7,0x00] ; AVX-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; AVX-NEXT: retl ## encoding: [0xc3] @@ -1997,8 +1891,8 @@ define void @movnt_dq(i8* %p, <2 x i64> %a1) nounwind { ; AVX512VL-LABEL: movnt_dq: ; AVX512VL: ## BB#0: ; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04] -; AVX512VL-NEXT: vpaddq LCPI136_0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd4,0x05,A,A,A,A] -; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI136_0, kind: FK_Data_4 +; AVX512VL-NEXT: vpaddq LCPI127_0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd4,0x05,A,A,A,A] +; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI127_0, kind: FK_Data_4 ; AVX512VL-NEXT: vmovntdq %ymm0, (%eax) ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe7,0x00] ; AVX512VL-NEXT: retl ## encoding: [0xc3] %a2 = add <2 x i64> %a1, diff --git a/test/CodeGen/X86/sse3-intrinsics-x86.ll b/test/CodeGen/X86/sse3-intrinsics-x86.ll index 362525f24d2..fd7f59a0157 100644 --- a/test/CodeGen/X86/sse3-intrinsics-x86.ll +++ b/test/CodeGen/X86/sse3-intrinsics-x86.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse3 -show-mc-encoding | FileCheck %s --check-prefix=SSE -; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+avx2 -show-mc-encoding | FileCheck %s --check-prefix=VCHECK --check-prefix=AVX2 -; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=skx -show-mc-encoding | FileCheck %s --check-prefix=VCHECK --check-prefix=SKX +; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse3 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=SSE +; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+avx2 -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=VCHECK --check-prefix=AVX2 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=skx -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=VCHECK --check-prefix=SKX define <2 x double> @test_x86_sse3_addsub_pd(<2 x double> %a0, <2 x double> %a1) { ; SSE-LABEL: test_x86_sse3_addsub_pd: @@ -115,3 +115,31 @@ define <16 x i8> @test_x86_sse3_ldu_dq(i8* %a0) { ret <16 x i8> %res } declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8*) nounwind readonly + +; Make sure instructions with no AVX equivalents, but are associated with SSEX feature flags still work + +define void @monitor(i8* %P, i32 %E, i32 %H) nounwind { +; CHECK-LABEL: monitor: +; CHECK: ## BB#0: +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx ## encoding: [0x8b,0x54,0x24,0x0c] +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x08] +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04] +; CHECK-NEXT: leal (%eax), %eax ## encoding: [0x8d,0x00] +; CHECK-NEXT: monitor ## encoding: [0x0f,0x01,0xc8] +; CHECK-NEXT: retl ## encoding: [0xc3] + tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H) + ret void +} +declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind + +define void @mwait(i32 %E, i32 %H) nounwind { +; CHECK-LABEL: mwait: +; CHECK: ## BB#0: +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ## encoding: [0x8b,0x4c,0x24,0x04] +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08] +; CHECK-NEXT: mwait ## encoding: [0x0f,0x01,0xc9] +; CHECK-NEXT: retl ## encoding: [0xc3] + tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H) + ret void +} +declare void @llvm.x86.sse3.mwait(i32, i32) nounwind -- 2.50.1