From c31f9e0d7156d497dc2e6a81eff0c0ed0809ac5b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 2 Oct 2017 20:31:16 +0000 Subject: [PATCH] AMDGPU: Fix potentially incorrectly matching check lines These check lines are supposed to make sure the new d16 load instructions aren't used, but the expected instruction name is a prefix of the incorrect instruction name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314714 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/AMDGPU/load-hi16.ll | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/test/CodeGen/AMDGPU/load-hi16.ll b/test/CodeGen/AMDGPU/load-hi16.ll index 806664bb32e..88a60935c74 100644 --- a/test/CodeGen/AMDGPU/load-hi16.ll +++ b/test/CodeGen/AMDGPU/load-hi16.ll @@ -7,7 +7,7 @@ ; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_setpc_b64 -; VI: ds_read_u16 +; VI: ds_read_u16 v define <2 x i16> @load_local_hi_v2i16_undeflo(i16 addrspace(3)* %in) #0 { entry: %load = load i16, i16 addrspace(3)* %in @@ -22,7 +22,7 @@ entry: ; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: s_setpc_b64 -; VI: ds_read_u16 +; VI: ds_read_u16 v define <2 x i16> @load_local_hi_v2i16_reglo(i16 addrspace(3)* %in, i16 %reg) #0 { entry: %load = load i16, i16 addrspace(3)* %in @@ -40,7 +40,7 @@ entry: ; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_setpc_b64 -; VI: ds_read_u16 +; VI: ds_read_u16 v define void @load_local_hi_v2i16_reglo_vreg(i16 addrspace(3)* %in, i16 %reg) #0 { entry: %load = load i16, i16 addrspace(3)* %in @@ -58,7 +58,7 @@ entry: ; GFX9-NEXT: v_mov_b32_e32 v0, v1 ; GFX9-NEXT: s_setpc_b64 -; VI: ds_read_u16 +; VI: ds_read_u16 v define <2 x i16> @load_local_hi_v2i16_zerolo(i16 addrspace(3)* %in) #0 { entry: %load = load i16, i16 addrspace(3)* %in @@ -75,7 +75,7 @@ entry: ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX9-NEXT: s_setpc_b64 -; VI: ds_read_u16 +; VI: ds_read_u16 v ; VI: v_lshlrev_b32_e32 v0, 16, v0 define i32 @load_local_hi_v2i16_zerolo_shift(i16 addrspace(3)* %in) #0 { entry: @@ -93,7 +93,7 @@ entry: ; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_setpc_b64 -; VI: ds_read_u16 +; VI: ds_read_u16 v define void @load_local_hi_v2f16_reglo_vreg(half addrspace(3)* %in, half %reg) #0 { entry: %load = load half, half addrspace(3)* %in @@ -111,7 +111,7 @@ entry: ; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_setpc_b64 -; VI: ds_read_u8 +; VI: ds_read_u8 v define void @load_local_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(3)* %in, i16 %reg) #0 { entry: %load = load i8, i8 addrspace(3)* %in @@ -130,7 +130,7 @@ entry: ; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_setpc_b64 -; VI: ds_read_i8 +; VI: ds_read_i8 v define void @load_local_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(3)* %in, i16 %reg) #0 { entry: %load = load i8, i8 addrspace(3)* %in -- 2.40.0