From c1af14f0c1ca2fd5606eb5c1f4a370606952bc32 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Tue, 7 Mar 2017 14:20:19 +0000 Subject: [PATCH] [Hexagon] Do not insert instructions before PHI nodes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297141 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonBitSimplify.cpp | 4 +++- test/CodeGen/Hexagon/bit-phi.ll | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/Target/Hexagon/HexagonBitSimplify.cpp b/lib/Target/Hexagon/HexagonBitSimplify.cpp index 79787463684..a155762cd4a 100644 --- a/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -2375,7 +2375,9 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI, DebugLoc DL = MI->getDebugLoc(); MachineBasicBlock &B = *MI->getParent(); unsigned NewR = MRI.createVirtualRegister(FRC); - auto MIB = BuildMI(B, MI, DL, HII.get(ExtOpc), NewR) + auto At = MI->isPHI() ? B.getFirstNonPHI() + : MachineBasicBlock::iterator(MI); + auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) .addReg(R, 0, SR); switch (ExtOpc) { case Hexagon::A2_sxtb: diff --git a/test/CodeGen/Hexagon/bit-phi.ll b/test/CodeGen/Hexagon/bit-phi.ll index 86b18d8bf25..7abfba079bb 100644 --- a/test/CodeGen/Hexagon/bit-phi.ll +++ b/test/CodeGen/Hexagon/bit-phi.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=hexagon < %s +; RUN: llc -march=hexagon -disable-hcp < %s ; REQUIRES: asserts target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32" -- 2.50.1