From c02caf5200ae866034fbf5db39df73f4b11df5bb Mon Sep 17 00:00:00 2001 From: Eugene Zelenko Date: Wed, 30 Nov 2016 17:48:10 +0000 Subject: [PATCH] Fix some Clang-tidy and Include What You Use warnings; other minor fixes (NFC). This preparation to remove SetVector.h dependency on SmallSet.h. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288256 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Analysis/LoopAccessAnalysis.cpp | 49 +++++++- lib/ExecutionEngine/Orc/OrcMCJITReplacement.h | 31 +++++- lib/Transforms/Scalar/LoopLoadElimination.cpp | 29 ++++- lib/Transforms/Scalar/LoopStrengthReduce.cpp | 88 ++++++++++----- lib/Transforms/Utils/SimplifyCFG.cpp | 57 ++++++++-- utils/TableGen/AsmWriterEmitter.cpp | 55 ++++++--- utils/TableGen/CodeEmitterGen.cpp | 22 ++-- utils/TableGen/CodeGenRegisters.cpp | 50 +++++++-- utils/TableGen/CodeGenRegisters.h | 31 ++++-- utils/TableGen/CodeGenSchedule.cpp | 43 ++++--- utils/TableGen/DFAPacketizerEmitter.cpp | 45 ++++---- utils/TableGen/FixedLenDecoderEmitter.cpp | 105 ++++++++++-------- 12 files changed, 426 insertions(+), 179 deletions(-) diff --git a/lib/Analysis/LoopAccessAnalysis.cpp b/lib/Analysis/LoopAccessAnalysis.cpp index a775f15ced9..01a2f464038 100644 --- a/lib/Analysis/LoopAccessAnalysis.cpp +++ b/lib/Analysis/LoopAccessAnalysis.cpp @@ -12,19 +12,61 @@ // //===----------------------------------------------------------------------===// +#include "llvm/ADT/APInt.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/EquivalenceClasses.h" +#include "llvm/ADT/iterator_range.h" +#include "llvm/ADT/PointerIntPair.h" +#include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/Analysis/AliasAnalysis.h" +#include "llvm/Analysis/AliasSetTracker.h" #include "llvm/Analysis/LoopAccessAnalysis.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/LoopPassManager.h" +#include "llvm/Analysis/MemoryLocation.h" #include "llvm/Analysis/OptimizationDiagnosticInfo.h" +#include "llvm/Analysis/ScalarEvolution.h" #include "llvm/Analysis/ScalarEvolutionExpander.h" +#include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/Analysis/TargetLibraryInfo.h" #include "llvm/Analysis/ValueTracking.h" #include "llvm/Analysis/VectorUtils.h" +#include "llvm/IR/BasicBlock.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/DebugLoc.h" +#include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/DiagnosticInfo.h" #include "llvm/IR/Dominators.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/InstrTypes.h" +#include "llvm/IR/Instruction.h" +#include "llvm/IR/Instructions.h" #include "llvm/IR/IRBuilder.h" +#include "llvm/IR/Operator.h" #include "llvm/IR/PassManager.h" +#include "llvm/IR/Type.h" +#include "llvm/IR/Value.h" +#include "llvm/IR/ValueHandle.h" +#include "llvm/Pass.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include +#include +#include +#include +#include +#include +#include + using namespace llvm; #define DEBUG_TYPE "loop-accesses" @@ -467,6 +509,7 @@ void RuntimePointerChecking::print(raw_ostream &OS, unsigned Depth) const { } namespace { + /// \brief Analyses memory accesses in a loop. /// /// Checks whether run time pointer checks are needed and builds sets for data @@ -1806,6 +1849,7 @@ static Instruction *getFirstInst(Instruction *FirstInst, Value *V, } namespace { + /// \brief IR Values for the lower and upper bounds of a pointer evolution. We /// need to use value-handles because SCEV expansion can invalidate previously /// expanded values. Thus expansion of a pointer can invalidate the bounds for @@ -1814,6 +1858,7 @@ struct PointerBounds { TrackingVH Start; TrackingVH End; }; + } // end anonymous namespace /// \brief Expand code for the lower and upper bound of the pointer group \p CG @@ -2101,7 +2146,9 @@ PreservedAnalyses LoopAccessInfoPrinterPass::run(Loop &L, } namespace llvm { + Pass *createLAAPass() { return new LoopAccessLegacyAnalysis(); } -} + +} // end namespace llvm diff --git a/lib/ExecutionEngine/Orc/OrcMCJITReplacement.h b/lib/ExecutionEngine/Orc/OrcMCJITReplacement.h index db9c519b826..af70960a1f9 100644 --- a/lib/ExecutionEngine/Orc/OrcMCJITReplacement.h +++ b/lib/ExecutionEngine/Orc/OrcMCJITReplacement.h @@ -14,18 +14,40 @@ #ifndef LLVM_LIB_EXECUTIONENGINE_ORC_ORCMCJITREPLACEMENT_H #define LLVM_LIB_EXECUTIONENGINE_ORC_ORCMCJITREPLACEMENT_H +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringRef.h" #include "llvm/ExecutionEngine/ExecutionEngine.h" +#include "llvm/ExecutionEngine/GenericValue.h" +#include "llvm/ExecutionEngine/JITSymbol.h" +#include "llvm/ExecutionEngine/RuntimeDyld.h" #include "llvm/ExecutionEngine/Orc/CompileUtils.h" #include "llvm/ExecutionEngine/Orc/IRCompileLayer.h" #include "llvm/ExecutionEngine/Orc/LazyEmittingLayer.h" #include "llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/Mangler.h" #include "llvm/Object/Archive.h" +#include "llvm/Object/Binary.h" +#include "llvm/Object/ObjectFile.h" +#include "llvm/Support/Error.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetMachine.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include namespace llvm { namespace orc { class OrcMCJITReplacement : public ExecutionEngine { - // OrcMCJITReplacement needs to do a little extra book-keeping to ensure that // Orc's automatic finalization doesn't kick in earlier than MCJIT clients are // expecting - see finalizeMemory. @@ -243,7 +265,6 @@ public: } private: - JITSymbol findMangledSymbol(StringRef Name) { if (auto Sym = LazyEmitLayer.findSymbol(Name, false)) return Sym; @@ -306,7 +327,6 @@ private: } private: - static const object::ObjectFile& getObject(const object::ObjectFile &Obj) { return Obj; } @@ -323,6 +343,7 @@ private: class NotifyFinalizedT { public: NotifyFinalizedT(OrcMCJITReplacement &M) : M(M) {} + void operator()(ObjectLinkingLayerBase::ObjSetHandleT H) { M.UnfinalizedSections.erase(H); } @@ -374,7 +395,7 @@ private: std::vector> Archives; }; -} // End namespace orc. -} // End namespace llvm. +} // end namespace orc +} // end namespace llvm #endif // LLVM_LIB_EXECUTIONENGINE_ORC_MCJITREPLACEMENT_H diff --git a/lib/Transforms/Scalar/LoopLoadElimination.cpp b/lib/Transforms/Scalar/LoopLoadElimination.cpp index c586cb53f0e..8e83c4700aa 100644 --- a/lib/Transforms/Scalar/LoopLoadElimination.cpp +++ b/lib/Transforms/Scalar/LoopLoadElimination.cpp @@ -20,18 +20,37 @@ // //===----------------------------------------------------------------------===// +#include "llvm/ADT/APInt.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/SmallSet.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/Analysis/GlobalsModRef.h" #include "llvm/Analysis/LoopAccessAnalysis.h" #include "llvm/Analysis/LoopInfo.h" +#include "llvm/Analysis/ScalarEvolution.h" #include "llvm/Analysis/ScalarEvolutionExpander.h" +#include "llvm/Analysis/ScalarEvolutionExpressions.h" +#include "llvm/IR/DataLayout.h" #include "llvm/IR/Dominators.h" +#include "llvm/IR/Instructions.h" #include "llvm/IR/Module.h" +#include "llvm/IR/Type.h" +#include "llvm/IR/Value.h" #include "llvm/Pass.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils/LoopVersioning.h" #include +#include +#include +#include +#include +#include #define LLE_OPTION "loop-load-elim" #define DEBUG_TYPE LLE_OPTION @@ -48,7 +67,6 @@ static cl::opt LoadElimSCEVCheckThreshold( cl::desc("The maximum number of SCEV checks allowed for Loop " "Load Elimination")); - STATISTIC(NumLoopLoadEliminted, "Number of loads eliminated by LLE"); namespace { @@ -114,7 +132,7 @@ bool doesStoreDominatesAllLatches(BasicBlock *StoreBlock, Loop *L, DominatorTree *DT) { SmallVector Latches; L->getLoopLatches(Latches); - return all_of(Latches, [&](const BasicBlock *Latch) { + return llvm::all_of(Latches, [&](const BasicBlock *Latch) { return DT->dominates(StoreBlock, Latch); }); } @@ -586,7 +604,8 @@ public: static char ID; }; -} + +} // end anonymous namespace char LoopLoadElimination::ID; static const char LLE_name[] = "Loop Load Elimination"; @@ -600,7 +619,9 @@ INITIALIZE_PASS_DEPENDENCY(LoopSimplify) INITIALIZE_PASS_END(LoopLoadElimination, LLE_OPTION, LLE_name, false, false) namespace llvm { + FunctionPass *createLoopLoadEliminationPass() { return new LoopLoadElimination(); } -} + +} // end namespace llvm diff --git a/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/lib/Transforms/Scalar/LoopStrengthReduce.cpp index 3805d455a8a..2a378a43728 100644 --- a/lib/Transforms/Scalar/LoopStrengthReduce.cpp +++ b/lib/Transforms/Scalar/LoopStrengthReduce.cpp @@ -54,30 +54,63 @@ //===----------------------------------------------------------------------===// #include "llvm/Transforms/Scalar/LoopStrengthReduce.h" +#include "llvm/ADT/APInt.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/Hashing.h" -#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallBitVector.h" +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/Analysis/IVUsers.h" +#include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/LoopPass.h" #include "llvm/Analysis/LoopPassManager.h" +#include "llvm/Analysis/ScalarEvolution.h" #include "llvm/Analysis/ScalarEvolutionExpander.h" +#include "llvm/Analysis/ScalarEvolutionExpressions.h" +#include "llvm/Analysis/ScalarEvolutionNormalization.h" #include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/IR/BasicBlock.h" +#include "llvm/IR/Constant.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Dominators.h" +#include "llvm/IR/GlobalValue.h" +#include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/IntrinsicInst.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/OperandTraits.h" +#include "llvm/IR/Operator.h" #include "llvm/IR/Module.h" +#include "llvm/IR/Type.h" +#include "llvm/IR/Value.h" #include "llvm/IR/ValueHandle.h" +#include "llvm/Pass.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/Local.h" #include +#include +#include +#include +#include +#include +#include +#include +#include + using namespace llvm; #define DEBUG_TYPE "loop-reduce" @@ -141,7 +174,7 @@ public: void dump() const; }; -} +} // end anonymous namespace void RegSortData::print(raw_ostream &OS) const { OS << "[NumUses=" << UsedByIndices.count() << ']'; @@ -180,7 +213,7 @@ public: const_iterator end() const { return RegSequence.end(); } }; -} +} // end anonymous namespace void RegUseTracker::countRegister(const SCEV *Reg, size_t LUIdx) { @@ -212,7 +245,7 @@ RegUseTracker::swapAndDropUse(size_t LUIdx, size_t LastLUIdx) { SmallBitVector &UsedByIndices = Pair.second.UsedByIndices; if (LUIdx < UsedByIndices.size()) UsedByIndices[LUIdx] = - LastLUIdx < UsedByIndices.size() ? UsedByIndices[LastLUIdx] : 0; + LastLUIdx < UsedByIndices.size() ? UsedByIndices[LastLUIdx] : false; UsedByIndices.resize(std::min(UsedByIndices.size(), LastLUIdx)); } } @@ -303,7 +336,7 @@ struct Formula { void dump() const; }; -} +} // end anonymous namespace /// Recursion helper for initialMatch. static void DoInitialMatch(const SCEV *S, Loop *L, @@ -823,8 +856,10 @@ DeleteTriviallyDeadInstructions(SmallVectorImpl &DeadInsts) { } namespace { + class LSRUse; -} + +} // end anonymous namespace /// \brief Check if the addressing mode defined by \p F is completely /// folded in \p LU at isel time. @@ -931,7 +966,6 @@ struct LSRFixup { void dump() const; }; - /// A DenseMapInfo implementation for holding DenseMaps and DenseSets of sorted /// SmallVectors of const SCEV*. struct UniquifierDenseMapInfo { @@ -1040,7 +1074,7 @@ public: void dump() const; }; -} +} // end anonymous namespace /// Tally up interesting quantities from the given register. void Cost::RateRegister(const SCEV *Reg, @@ -1785,7 +1819,7 @@ public: void dump() const; }; -} +} // end anonymous namespace /// If IV is used in a int-to-float cast inside the loop then try to eliminate /// the cast operation. @@ -2518,7 +2552,7 @@ bool IVChain::isProfitableIncrement(const SCEV *OperExpr, if (!isa(IncExpr)) { const SCEV *HeadExpr = SE.getSCEV(getWideOperand(Incs[0].IVOperand)); if (isa(SE.getMinusSCEV(OperExpr, HeadExpr))) - return 0; + return false; } SmallPtrSet Processed; @@ -3650,7 +3684,7 @@ struct WorkItem { void dump() const; }; -} +} // end anonymous namespace void WorkItem::print(raw_ostream &OS) const { OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx @@ -4318,7 +4352,7 @@ LSRInstance::HoistInsertPosition(BasicBlock::iterator IP, const SmallVectorImpl &Inputs) const { Instruction *Tentative = &*IP; - for (;;) { + while (true) { bool AllDominate = true; Instruction *BetterPos = nullptr; // Don't bother attempting to insert before a catchswitch, their basic block @@ -4943,27 +4977,15 @@ namespace { class LoopStrengthReduce : public LoopPass { public: static char ID; // Pass ID, replacement for typeid + LoopStrengthReduce(); private: bool runOnLoop(Loop *L, LPPassManager &LPM) override; void getAnalysisUsage(AnalysisUsage &AU) const override; }; -} -char LoopStrengthReduce::ID = 0; -INITIALIZE_PASS_BEGIN(LoopStrengthReduce, "loop-reduce", - "Loop Strength Reduction", false, false) -INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass) -INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) -INITIALIZE_PASS_DEPENDENCY(ScalarEvolutionWrapperPass) -INITIALIZE_PASS_DEPENDENCY(IVUsersWrapperPass) -INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass) -INITIALIZE_PASS_DEPENDENCY(LoopSimplify) -INITIALIZE_PASS_END(LoopStrengthReduce, "loop-reduce", - "Loop Strength Reduction", false, false) - -Pass *llvm::createLoopStrengthReducePass() { return new LoopStrengthReduce(); } +} // end anonymous namespace LoopStrengthReduce::LoopStrengthReduce() : LoopPass(ID) { initializeLoopStrengthReducePass(*PassRegistry::getPassRegistry()); @@ -5048,3 +5070,17 @@ PreservedAnalyses LoopStrengthReducePass::run(Loop &L, return getLoopPassPreservedAnalyses(); } + +char LoopStrengthReduce::ID = 0; +INITIALIZE_PASS_BEGIN(LoopStrengthReduce, "loop-reduce", + "Loop Strength Reduction", false, false) +INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass) +INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) +INITIALIZE_PASS_DEPENDENCY(ScalarEvolutionWrapperPass) +INITIALIZE_PASS_DEPENDENCY(IVUsersWrapperPass) +INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass) +INITIALIZE_PASS_DEPENDENCY(LoopSimplify) +INITIALIZE_PASS_END(LoopStrengthReduce, "loop-reduce", + "Loop Strength Reduction", false, false) + +Pass *llvm::createLoopStrengthReducePass() { return new LoopStrengthReduce(); } diff --git a/lib/Transforms/Utils/SimplifyCFG.cpp b/lib/Transforms/Utils/SimplifyCFG.cpp index ec5db1e5744..323b81ca815 100644 --- a/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/lib/Transforms/Utils/SimplifyCFG.cpp @@ -11,27 +11,39 @@ // //===----------------------------------------------------------------------===// +#include "llvm/ADT/APInt.h" +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/Optional.h" #include "llvm/ADT/SetOperations.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/Analysis/ConstantFolding.h" #include "llvm/Analysis/EHPersonalities.h" #include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/ValueTracking.h" +#include "llvm/IR/BasicBlock.h" +#include "llvm/IR/CallSite.h" #include "llvm/IR/CFG.h" +#include "llvm/IR/Constant.h" #include "llvm/IR/ConstantRange.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DataLayout.h" +#include "llvm/IR/DebugLoc.h" #include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/GlobalValue.h" #include "llvm/IR/GlobalVariable.h" #include "llvm/IR/IRBuilder.h" +#include "llvm/IR/InstrTypes.h" +#include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/IntrinsicInst.h" +#include "llvm/IR/Intrinsics.h" #include "llvm/IR/LLVMContext.h" #include "llvm/IR/MDBuilder.h" #include "llvm/IR/Metadata.h" @@ -40,15 +52,28 @@ #include "llvm/IR/Operator.h" #include "llvm/IR/PatternMatch.h" #include "llvm/IR/Type.h" +#include "llvm/IR/User.h" +#include "llvm/IR/Value.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/ValueMapper.h" #include +#include +#include +#include +#include +#include #include #include +#include +#include + using namespace llvm; using namespace PatternMatch; @@ -110,6 +135,7 @@ STATISTIC(NumSinkCommons, STATISTIC(NumSpeculations, "Number of speculative executed instructions"); namespace { + // The first field contains the value that the switch produces when a certain // case group is selected, and the second field is a vector containing the // cases composing the case group. @@ -168,9 +194,11 @@ public: SmallPtrSetImpl *LoopHeaders) : TTI(TTI), DL(DL), BonusInstThreshold(BonusInstThreshold), AC(AC), LoopHeaders(LoopHeaders) {} + bool run(BasicBlock *BB); }; -} + +} // end anonymous namespace /// Return true if it is safe to merge these two /// terminator instructions together. @@ -627,7 +655,8 @@ private: } } }; -} + +} // end anonymous namespace static void EraseTerminatorInstAndDCECond(TerminatorInst *TI) { Instruction *Cond = nullptr; @@ -712,7 +741,7 @@ static bool ValuesOverlap(std::vector &C1, if (V1->size() > V2->size()) std::swap(V1, V2); - if (V1->size() == 0) + if (V1->empty()) return false; if (V1->size() == 1) { // Just scan V2. @@ -880,6 +909,7 @@ bool SimplifyCFGOpt::SimplifyEqualityComparisonWithOnlyPredecessor( } namespace { + /// This class implements a stable ordering of constant /// integers that does not depend on their address. This is important for /// applications that sort ConstantInt's to ensure uniqueness. @@ -888,7 +918,8 @@ struct ConstantIntOrdering { return LHS->getValue().ult(RHS->getValue()); } }; -} + +} // end anonymous namespace static int ConstantIntSortPredicate(ConstantInt *const *P1, ConstantInt *const *P2) { @@ -1568,6 +1599,7 @@ static bool sinkLastInstruction(ArrayRef Blocks) { } namespace { + // LockstepReverseIterator - Iterates through instructions // in a set of blocks in reverse order from the first non-terminator. // For example (assume all blocks have size n): @@ -1624,7 +1656,8 @@ namespace { return Insts; } }; -} + +} // end anonymous namespace /// Given an unconditional branch that goes to BBEnd, /// check whether BBEnd has only two predecessors and the other predecessor @@ -4520,7 +4553,7 @@ ConstantFold(Instruction *I, const DataLayout &DL, static bool GetCaseResults(SwitchInst *SI, ConstantInt *CaseVal, BasicBlock *CaseDest, BasicBlock **CommonDest, - SmallVectorImpl > &Res, + SmallVectorImpl> &Res, const DataLayout &DL, const TargetTransformInfo &TTI) { // The block from which we enter the common destination. BasicBlock *Pred = SI->getParent(); @@ -4748,6 +4781,7 @@ static bool SwitchToSelect(SwitchInst *SI, IRBuilder<> &Builder, } namespace { + /// This class represents a lookup table that can be used to replace a switch. class SwitchLookupTable { public: @@ -4804,7 +4838,8 @@ private: // For ArrayKind, this is the array. GlobalVariable *Array; }; -} + +} // end anonymous namespace SwitchLookupTable::SwitchLookupTable( Module &M, uint64_t TableSize, ConstantInt *Offset, @@ -5406,7 +5441,7 @@ static bool ReduceSwitchRange(SwitchInst *SI, IRBuilder<> &Builder, // is bitwise only, we switch now to an unsigned representation. uint64_t GCD = 0; for (auto &V : Values) - GCD = llvm::GreatestCommonDivisor64(GCD, (uint64_t)V); + GCD = GreatestCommonDivisor64(GCD, (uint64_t)V); // This transform can be done speculatively because it is so cheap - it results // in a single rotate operation being inserted. This can only happen if the @@ -5416,11 +5451,11 @@ static bool ReduceSwitchRange(SwitchInst *SI, IRBuilder<> &Builder, // FIXME: It's possible that optimizing a switch on powers of two might also // be beneficial - flag values are often powers of two and we could use a CLZ // as the key function. - if (GCD <= 1 || !llvm::isPowerOf2_64(GCD)) + if (GCD <= 1 || !isPowerOf2_64(GCD)) // No common divisor found or too expensive to compute key function. return false; - unsigned Shift = llvm::Log2_64(GCD); + unsigned Shift = Log2_64(GCD); for (auto &V : Values) V = (int64_t)((uint64_t)V >> Shift); diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index 70cea1fb930..5fab4a93b03 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -13,33 +13,53 @@ //===----------------------------------------------------------------------===// #include "AsmWriterInst.h" +#include "CodeGenInstruction.h" +#include "CodeGenRegisters.h" #include "CodeGenTarget.h" #include "SequenceToOffsetTable.h" #include "Types.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallString.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/StringRef.h" #include "llvm/ADT/Twine.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Format.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" #include #include +#include +#include +#include +#include #include +#include +#include +#include #include #include + using namespace llvm; #define DEBUG_TYPE "asm-writer-emitter" namespace { + class AsmWriterEmitter { RecordKeeper &Records; CodeGenTarget Target; ArrayRef NumberedInstructions; std::vector Instructions; + public: AsmWriterEmitter(RecordKeeper &R); @@ -55,10 +75,11 @@ private: std::vector &InstOpsUsed, bool PassSubtarget) const; }; + } // end anonymous namespace static void PrintCases(std::vector > &OpsToPrint, raw_ostream &O, + AsmWriterOperand>> &OpsToPrint, raw_ostream &O, bool PassSubtarget) { O << " case " << OpsToPrint.back().first << ":"; AsmWriterOperand TheOp = OpsToPrint.back().second; @@ -77,7 +98,6 @@ static void PrintCases(std::vector &Insts, @@ -116,7 +136,7 @@ static void EmitInstructions(std::vector &Insts, // emit a switch for just this operand now. O << " switch (MI->getOpcode()) {\n"; O << " default: llvm_unreachable(\"Unexpected opcode.\");\n"; - std::vector > OpsToPrint; + std::vector> OpsToPrint; OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" + FirstInst.CGI->TheDef->getName(), FirstInst.Operands[i])); @@ -141,7 +161,6 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, std::vector> &InstIdxs, std::vector &InstOpsUsed, bool PassSubtarget) const { - // This vector parallels UniqueOperandCommands, keeping track of which // instructions each case are used for. It is a comma separated string of // enums. @@ -158,7 +177,7 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, // Check to see if we already have 'Command' in UniqueOperandCommands. // If not, add it. - auto I = find(UniqueOperandCommands, Command); + auto I = llvm::find(UniqueOperandCommands, Command); if (I != UniqueOperandCommands.end()) { size_t idx = I - UniqueOperandCommands.begin(); InstrsForCase[idx] += ", "; @@ -225,7 +244,6 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, } } - static void UnescapeString(std::string &Str) { for (unsigned i = 0; i != Str.size(); ++i) { if (Str[i] == '\\' && i != Str.size()-1) { @@ -317,7 +335,7 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { std::vector> TableDrivenOperandPrinters; - while (1) { + while (true) { std::vector UniqueOperandCommands; std::vector> InstIdxs; std::vector NumInstOpsHandled; @@ -451,7 +469,7 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { } // Okay, delete instructions with no operand info left. - auto I = remove_if(Instructions, + auto I = llvm::remove_if(Instructions, [](AsmWriterInst &Inst) { return Inst.Operands.empty(); }); Instructions.erase(I, Instructions.end()); @@ -584,6 +602,7 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { } namespace { + // IAPrinter - Holds information about an InstAlias. Two InstAliases match if // they both have the same conditionals. In which case, we cannot print out the // alias for that pattern. @@ -593,6 +612,7 @@ class IAPrinter { std::string Result; std::string AsmString; + public: IAPrinter(std::string R, std::string AS) : Result(std::move(R)), AsmString(std::move(AS)) {} @@ -714,6 +734,7 @@ static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) { } namespace { + struct AliasPriorityComparator { typedef std::pair ValueType; bool operator()(const ValueType &LHS, const ValueType &RHS) { @@ -727,8 +748,8 @@ struct AliasPriorityComparator { return LHS.second > RHS.second; } }; -} +} // end anonymous namespace void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { Record *AsmWriter = Target.getAsmWriter(); @@ -803,14 +824,14 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { NumMIOps += Operand.getMINumOperands(); std::string Cond; - Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps); + Cond = std::string("MI->getNumOperands() == ") + utostr(NumMIOps); IAP.addCond(Cond); bool CantHandle = false; unsigned MIOpNum = 0; for (unsigned i = 0, e = LastOpNo; i != e; ++i) { - std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")"; + std::string Op = "MI->getOperand(" + utostr(MIOpNum) + ")"; const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i]; @@ -828,7 +849,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { std::string PrintMethod = Rec->getValueAsString("PrintMethod"); if (PrintMethod != "" && PrintMethod != "printOperand") { PrintMethodIdx = - find(PrintMethods, PrintMethod) - PrintMethods.begin(); + llvm::find(PrintMethods, PrintMethod) - PrintMethods.begin(); if (static_cast(PrintMethodIdx) == PrintMethods.size()) PrintMethods.push_back(PrintMethod); } @@ -849,7 +870,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { ".contains(" + Op + ".getReg())"; } else { Cond = Op + ".getReg() == MI->getOperand(" + - llvm::utostr(IAP.getOpIndex(ROName)) + ").getReg()"; + utostr(IAP.getOpIndex(ROName)) + ").getReg()"; } } else { // Assume all printable operands are desired for now. This can be @@ -867,7 +888,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { break; // No conditions on this operand at all } Cond = Target.getName() + ClassName + "ValidateMCOperand(" + - Op + ", STI, " + llvm::utostr(Entry) + ")"; + Op + ", STI, " + utostr(Entry) + ")"; } // for all subcases of ResultOperand::K_Record: IAP.addCond(Cond); @@ -878,8 +899,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { // MCInst will. An MCExpr could be present, for example. IAP.addCond(Op + ".isImm()"); - Cond = Op + ".getImm() == " + - llvm::itostr(CGA.ResultOperands[i].getImm()); + Cond = Op + ".getImm() == " + itostr(CGA.ResultOperands[i].getImm()); IAP.addCond(Cond); break; } @@ -1100,7 +1120,6 @@ void AsmWriterEmitter::run(raw_ostream &O) { EmitPrintAliasInstruction(O); } - namespace llvm { void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) { @@ -1108,4 +1127,4 @@ void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) { AsmWriterEmitter(RK).run(OS); } -} // End llvm namespace +} // end namespace llvm diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index 9bcdebd9548..fc2e5aa919e 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -13,26 +13,35 @@ // //===----------------------------------------------------------------------===// +#include "CodeGenInstruction.h" #include "CodeGenTarget.h" #include "SubtargetFeatureInfo.h" -#include "Types.h" +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/Support/Debug.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" +#include +#include #include +#include #include +#include #include + using namespace llvm; namespace { class CodeEmitterGen { RecordKeeper &Records; + public: CodeEmitterGen(RecordKeeper &R) : Records(R) {} void run(raw_ostream &o); + private: int getVariableBit(const std::string &VarName, BitsInit *BI, int bit); std::string getInstructionCase(Record *R, CodeGenTarget &Target); @@ -175,7 +184,6 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, } } - std::string CodeEmitterGen::getInstructionCase(Record *R, CodeGenTarget &Target) { std::string Case; @@ -261,7 +269,7 @@ void CodeEmitterGen::run(raw_ostream &o) { o << " UINT64_C(0)\n };\n"; // Map to accumulate all the cases. - std::map > CaseMap; + std::map> CaseMap; // Construct all cases statement for each opcode for (std::vector::iterator IC = Insts.begin(), EC = Insts.end(); @@ -285,7 +293,7 @@ void CodeEmitterGen::run(raw_ostream &o) { << " switch (opcode) {\n"; // Emit each case statement - std::map >::iterator IE, EE; + std::map>::iterator IE, EE; for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) { const std::string &Case = IE->first; std::vector &InstList = IE->second; @@ -374,7 +382,7 @@ void CodeEmitterGen::run(raw_ostream &o) { o << "#endif\n"; } -} // End anonymous namespace +} // end anonymous namespace namespace llvm { @@ -383,4 +391,4 @@ void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) { CodeEmitterGen(RK).run(OS); } -} // End llvm namespace +} // end namespace llvm diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index 8eeed811c43..9fc139245f3 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -14,13 +14,33 @@ #include "CodeGenRegisters.h" #include "CodeGenTarget.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/IntEqClasses.h" -#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/SparseBitVector.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/StringRef.h" #include "llvm/ADT/Twine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/TableGen/Error.h" +#include "llvm/TableGen/Record.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include using namespace llvm; @@ -151,6 +171,7 @@ const std::string &CodeGenRegister::getName() const { } namespace { + // Iterate over all register units in a set of registers. class RegUnitIterator { CodeGenRegister::Vec::const_iterator RegI, RegE; @@ -158,7 +179,7 @@ class RegUnitIterator { public: RegUnitIterator(const CodeGenRegister::Vec &Regs): - RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() { + RegI(Regs.begin()), RegE(Regs.end()) { if (RegI != RegE) { UnitI = (*RegI)->getRegUnits().begin(); @@ -190,7 +211,8 @@ protected: } } }; -} // namespace + +} // end anonymous namespace // Return true of this unit appears in RegUnits. static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) { @@ -538,6 +560,7 @@ unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const { // sub-registers. We provide a SetTheory expander class that returns the new // registers. namespace { + struct TupleExpander : SetTheory::Expander { void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override { std::vector Indices = Def->getValueAsListOfDefs("SubRegIndices"); @@ -639,7 +662,8 @@ struct TupleExpander : SetTheory::Expander { } } }; -} + +} // end anonymous namespace //===----------------------------------------------------------------------===// // CodeGenRegisterClass @@ -767,13 +791,15 @@ bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const { } namespace llvm { + raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) { OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment; for (const auto R : *K.Members) OS << ", " << R->getName(); return OS << " }"; } -} + +} // end namespace llvm // This is a simple lexicographical order that can be used to search for sets. // It is not the same as the topological order provided by TopoOrderRC. @@ -813,7 +839,7 @@ static bool TopoOrderRC(const CodeGenRegisterClass &PA, auto *A = &PA; auto *B = &PB; if (A == B) - return 0; + return false; // Order by ascending spill size. if (A->SpillSize < B->SpillSize) @@ -1289,6 +1315,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() { } namespace { + // UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is // the transitive closure of the union of overlapping register // classes. Together, the UberRegSets form a partition of the registers. If we @@ -1307,12 +1334,13 @@ namespace { // their weight increased. struct UberRegSet { CodeGenRegister::Vec Regs; - unsigned Weight; + unsigned Weight = 0; CodeGenRegister::RegUnitList SingularDeterminants; - UberRegSet(): Weight(0) {} + UberRegSet() = default; }; -} // namespace + +} // end anonymous namespace // Partition registers into UberRegSets, where each set is the transitive // closure of the union of overlapping register classes. @@ -1321,7 +1349,6 @@ struct UberRegSet { static void computeUberSets(std::vector &UberSets, std::vector &RegSets, CodeGenRegBank &RegBank) { - const auto &Registers = RegBank.getRegisters(); // The Register EnumValue is one greater than its index into Registers. @@ -1789,7 +1816,7 @@ void CodeGenRegBank::computeRegUnitLaneMasks() { CodeGenRegister *SubReg = S->second; // Ignore non-leaf subregisters, their lane masks are fully covered by // the leaf subregisters anyway. - if (SubReg->getSubRegs().size() != 0) + if (!SubReg->getSubRegs().empty()) continue; CodeGenSubRegIndex *SubRegIndex = S->first; const CodeGenRegister *SubRegister = S->second; @@ -2008,7 +2035,6 @@ void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC, } } - // // Infer missing register classes. // diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index b8d47aa4ff8..827eef8cf66 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -18,20 +18,28 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SparseBitVector.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringMap.h" +#include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/MachineValueType.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/SetTheory.h" -#include +#include +#include #include #include #include #include +#include #include namespace llvm { + class CodeGenRegBank; template class SetVector; @@ -41,6 +49,7 @@ namespace llvm { struct MaskRolPair { unsigned Mask; uint8_t RotateLeft; + bool operator==(const MaskRolPair Other) const { return Mask == Other.Mask && RotateLeft == Other.RotateLeft; } @@ -266,7 +275,7 @@ namespace llvm { class CodeGenRegisterClass { CodeGenRegister::Vec Members; // Allocation orders. Order[0] always contains all registers in Members. - std::vector > Orders; + std::vector> Orders; // Bit mask of sub-classes including this, indexed by their EnumValue. BitVector SubClasses; // List of super-classes, topologocally ordered to have the larger classes @@ -463,10 +472,10 @@ namespace llvm { std::string Name; std::vector Units; - unsigned Weight; // Cache the sum of all unit weights. - unsigned Order; // Cache the sort key. + unsigned Weight = 0; // Cache the sum of all unit weights. + unsigned Order = 0; // Cache the sort key. - RegUnitSet() : Weight(0), Order(0) {} + RegUnitSet() = default; }; // Base vector for identifying TopoSigs. The contents uniquely identify a @@ -515,7 +524,7 @@ namespace llvm { // NOTE: This could grow beyond the number of register classes when we map // register units to lists of unit sets. If the list of unit sets does not // already exist for a register class, we create a new entry in this vector. - std::vector > RegClassUnitSets; + std::vector> RegClassUnitSets; // Give each register unit set an order based on sorting criteria. std::vector RegUnitSetOrder; @@ -532,6 +541,7 @@ namespace llvm { void computeInferredRegisterClasses(); void inferCommonSubClass(CodeGenRegisterClass *RC); void inferSubClassWithSubReg(CodeGenRegisterClass *RC); + void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) { inferMatchingSuperRegClass(RC, RegClasses.begin()); } @@ -590,6 +600,7 @@ namespace llvm { } const std::deque &getRegisters() { return Registers; } + const StringMap &getRegistersByName() { return RegistersByName; } @@ -674,6 +685,7 @@ namespace llvm { unsigned getRegSetIDAt(unsigned Order) const { return RegUnitSetOrder[Order]; } + const RegUnitSet &getRegSetAt(unsigned Order) const { return RegUnitSets[RegUnitSetOrder[Order]]; } @@ -723,6 +735,7 @@ namespace llvm { // another sub-register with the same or larger lane mask. unsigned CoveringLanes; }; -} -#endif +} // end namespace llvm + +#endif // LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp index 4cc600d059b..cae1cf4b861 100644 --- a/utils/TableGen/CodeGenSchedule.cpp +++ b/utils/TableGen/CodeGenSchedule.cpp @@ -12,12 +12,21 @@ // //===----------------------------------------------------------------------===// +#include "CodeGenInstruction.h" #include "CodeGenSchedule.h" #include "CodeGenTarget.h" +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallSet.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Support/Regex.h" #include "llvm/TableGen/Error.h" +#include +#include +#include using namespace llvm; @@ -31,6 +40,7 @@ static void dumpIdxVec(ArrayRef V) { #endif namespace { + // (instrs a, b, ...) Evaluate and union all arguments. Identical to AddOp. struct InstrsOp : public SetTheory::Operator { void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts, @@ -76,6 +86,7 @@ struct InstRegexOp : public SetTheory::Operator { } } }; + } // end anonymous namespace /// CodeGenModels ctor interprets machine model records and populates maps. @@ -364,6 +375,7 @@ bool CodeGenSchedModels::hasReadOfWrite(Record *WriteDef) const { } namespace llvm { + void splitSchedReadWrites(const RecVec &RWDefs, RecVec &WriteDefs, RecVec &ReadDefs) { for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end(); RWI != RWE; ++RWI) { @@ -375,7 +387,8 @@ void splitSchedReadWrites(const RecVec &RWDefs, } } } -} // namespace llvm + +} // end namespace llvm // Split the SchedReadWrites defs and call findRWs for each list. void CodeGenSchedModels::findRWs(const RecVec &RWDefs, @@ -676,7 +689,7 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) { // intersects with an existing class via a previous InstRWDef. Instrs that do // not intersect with an existing class refer back to their former class as // determined from ItinDef or SchedRW. - SmallVector >, 4> ClassInstrs; + SmallVector>, 4> ClassInstrs; // Sort Instrs into sets. const RecVec *InstDefs = Sets.expand(InstRWDef); if (InstDefs->empty()) @@ -915,6 +928,7 @@ void CodeGenSchedModels::inferFromInstRWs(unsigned SCIdx) { } namespace { + // Helper for substituteVariantOperand. struct TransVariant { Record *VarOrSeqDef; // Variant or sequence. @@ -971,7 +985,8 @@ private: std::vector &IntersectingVariants); void pushVariant(const TransVariant &VInfo, bool IsRead); }; -} // anonymous + +} // end anonymous namespace // Return true if this predicate is mutually exclusive with a PredTerm. This // degenerates into checking if the predicate is mutually exclusive with any @@ -984,7 +999,6 @@ private: // conditions implicitly negate any prior condition. bool PredTransitions::mutuallyExclusive(Record *PredDef, ArrayRef Term) { - for (ArrayRef::iterator I = Term.begin(), E = Term.end(); I != E; ++I) { if (I->Predicate == PredDef) @@ -1031,7 +1045,7 @@ static bool hasVariant(ArrayRef Transitions, for (ArrayRef::iterator PTI = Transitions.begin(), PTE = Transitions.end(); PTI != PTE; ++PTI) { - for (SmallVectorImpl >::const_iterator + for (SmallVectorImpl>::const_iterator WSI = PTI->WriteSequences.begin(), WSE = PTI->WriteSequences.end(); WSI != WSE; ++WSI) { for (SmallVectorImpl::const_iterator @@ -1040,7 +1054,7 @@ static bool hasVariant(ArrayRef Transitions, return true; } } - for (SmallVectorImpl >::const_iterator + for (SmallVectorImpl>::const_iterator RSI = PTI->ReadSequences.begin(), RSE = PTI->ReadSequences.end(); RSI != RSE; ++RSI) { for (SmallVectorImpl::const_iterator @@ -1147,7 +1161,6 @@ void PredTransitions::getIntersectingVariants( // specified by VInfo. void PredTransitions:: pushVariant(const TransVariant &VInfo, bool IsRead) { - PredTransition &Trans = TransVec[VInfo.TransVecIdx]; // If this operand transition is reached through a processor-specific alias, @@ -1170,7 +1183,7 @@ pushVariant(const TransVariant &VInfo, bool IsRead) { const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(VInfo.RWIdx, IsRead); - SmallVectorImpl > &RWSequences = IsRead + SmallVectorImpl> &RWSequences = IsRead ? Trans.ReadSequences : Trans.WriteSequences; if (SchedRW.IsVariadic) { unsigned OperIdx = RWSequences.size()-1; @@ -1266,7 +1279,7 @@ void PredTransitions::substituteVariants(const PredTransition &Trans) { TransVec.back().ProcIndices = Trans.ProcIndices; // Visit each original write sequence. - for (SmallVectorImpl >::const_iterator + for (SmallVectorImpl>::const_iterator WSI = Trans.WriteSequences.begin(), WSE = Trans.WriteSequences.end(); WSI != WSE; ++WSI) { // Push a new (empty) write sequence onto all partial Transitions. @@ -1277,7 +1290,7 @@ void PredTransitions::substituteVariants(const PredTransition &Trans) { substituteVariantOperand(*WSI, /*IsRead=*/false, StartIdx); } // Visit each original read sequence. - for (SmallVectorImpl >::const_iterator + for (SmallVectorImpl>::const_iterator RSI = Trans.ReadSequences.begin(), RSE = Trans.ReadSequences.end(); RSI != RSE; ++RSI) { // Push a new (empty) read sequence onto all partial Transitions. @@ -1298,7 +1311,7 @@ static void inferFromTransitions(ArrayRef LastTransitions, for (ArrayRef::iterator I = LastTransitions.begin(), E = LastTransitions.end(); I != E; ++I) { IdxVec OperWritesVariant; - for (SmallVectorImpl >::const_iterator + for (SmallVectorImpl>::const_iterator WSI = I->WriteSequences.begin(), WSE = I->WriteSequences.end(); WSI != WSE; ++WSI) { // Create a new write representing the expanded sequence. @@ -1306,7 +1319,7 @@ static void inferFromTransitions(ArrayRef LastTransitions, SchedModels.findOrInsertRW(*WSI, /*IsRead=*/false)); } IdxVec OperReadsVariant; - for (SmallVectorImpl >::const_iterator + for (SmallVectorImpl>::const_iterator RSI = I->ReadSequences.begin(), RSE = I->ReadSequences.end(); RSI != RSE; ++RSI) { // Create a new read representing the expanded sequence. @@ -1658,7 +1671,6 @@ void CodeGenSchedModels::collectRWResources(unsigned RWIdx, bool IsRead, void CodeGenSchedModels::collectRWResources(ArrayRef Writes, ArrayRef Reads, ArrayRef ProcIndices) { - for (unsigned Idx : Writes) collectRWResources(Idx, /*IsRead=*/false, ProcIndices); @@ -1666,7 +1678,6 @@ void CodeGenSchedModels::collectRWResources(ArrayRef Writes, collectRWResources(Idx, /*IsRead=*/true, ProcIndices); } - // Find the processor's resource units for this kind of resource. Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind, const CodeGenProcModel &PM) const { @@ -1714,7 +1725,7 @@ Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind, // Iteratively add a resource and its super resources. void CodeGenSchedModels::addProcResource(Record *ProcResKind, CodeGenProcModel &PM) { - for (;;) { + while (true) { Record *ProcResUnits = findProcResUnits(ProcResKind, PM); // See if this ProcResource is already associated with this processor. @@ -1835,7 +1846,7 @@ void PredTransitions::dump() const { << ":" << PCI->Predicate->getName(); } dbgs() << "},\n => {"; - for (SmallVectorImpl >::const_iterator + for (SmallVectorImpl>::const_iterator WSI = TI->WriteSequences.begin(), WSE = TI->WriteSequences.end(); WSI != WSE; ++WSI) { dbgs() << "("; diff --git a/utils/TableGen/DFAPacketizerEmitter.cpp b/utils/TableGen/DFAPacketizerEmitter.cpp index e31caaf3c98..f879a5bae21 100644 --- a/utils/TableGen/DFAPacketizerEmitter.cpp +++ b/utils/TableGen/DFAPacketizerEmitter.cpp @@ -19,14 +19,18 @@ #include "CodeGenTarget.h" #include "llvm/ADT/DenseSet.h" -#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" +#include +#include #include +#include #include -#include +#include using namespace llvm; @@ -58,6 +62,7 @@ typedef int64_t DFAStateInput; #define DFA_TBLTYPE "int64_t" // For generating DFAStateInputTable. namespace { + DFAInput addDFAFuncUnits(DFAInput Inp, unsigned FuncUnits) { return (Inp << DFA_MAX_RESOURCES) | FuncUnits; } @@ -67,12 +72,13 @@ namespace { /// DFAPacketizerEmitter.cpp. DFAInput getDFAInsnInput(const std::vector &InsnClass) { DFAInput InsnInput = 0; - assert ((InsnClass.size() <= DFA_MAX_RESTERMS) && - "Exceeded maximum number of DFA terms"); + assert((InsnClass.size() <= DFA_MAX_RESTERMS) && + "Exceeded maximum number of DFA terms"); for (auto U : InsnClass) InsnInput = addDFAFuncUnits(InsnInput, U); return InsnInput; } + } // end anonymous namespace // -------------------------------------------------------------------- @@ -98,6 +104,7 @@ void dbgsIndent(unsigned indent); // for resource tracking. // namespace { + class DFAPacketizerEmitter { private: std::string TargetName; @@ -150,9 +157,7 @@ public: void run(raw_ostream &OS); }; -} // end anonymous namespace -// // // State represents the usage of machine resources if the packet contains // a set of instruction classes. @@ -174,7 +179,6 @@ public: // A State instance also contains a collection of transitions from that state: // a map from inputs to new states. // -namespace { class State { public: static int currentStateNum; @@ -204,6 +208,7 @@ class State { // bool canMaybeAddInsnClass(std::vector &InsnClass, std::map &ComboBitToBitsMap) const; + // // AddInsnClass - Return all combinations of resource reservation // which are possible from this state (PossibleStates). @@ -214,6 +219,7 @@ class State { void AddInsnClass(std::vector &InsnClass, std::map &ComboBitToBitsMap, std::set &PossibleStates) const; + // // AddInsnClassStages - Return all combinations of resource reservation // resulting from the cross product of all stages for this InsnClass @@ -225,31 +231,31 @@ class State { unsigned prevState, unsigned origState, DenseSet &VisitedResourceStates, std::set &PossibleStates) const; + // // addTransition - Add a transition from this state given the input InsnClass // void addTransition(std::vector InsnClass, const State *To) const; + // // hasTransition - Returns true if there is a transition from this state // given the input InsnClass // bool hasTransition(std::vector InsnClass) const; }; -} // end anonymous namespace // // class DFA: deterministic finite automaton for processor resource tracking. // -namespace { class DFA { public: - DFA(); + DFA() = default; // Set of states. Need to keep this sorted to emit the transition table. typedef std::set StateSet; StateSet states; - State *currentState; + State *currentState = nullptr; // // Modify the DFA. @@ -263,6 +269,7 @@ public: int numInsnClasses = 0, int maxResources = 0, int numCombos = 0, int maxStages = 0); }; + } // end anonymous namespace #ifndef NDEBUG @@ -314,8 +321,6 @@ void dbgsIndent(unsigned indent) { State::State() : stateNum(currentStateNum++), isInitial(false) {} -DFA::DFA(): currentState(nullptr) {} - // // addTransition - Add a transition from this state given the input InsnClass // @@ -370,7 +375,6 @@ void State::AddInsnClassStages(std::vector &InsnClass, unsigned prevState, unsigned origState, DenseSet &VisitedResourceStates, std::set &PossibleStates) const { - assert((chkstage < numstages) && "AddInsnClassStages: stage out of range"); unsigned thisStage = InsnClass[chkstage]; @@ -469,7 +473,6 @@ bool State::canMaybeAddInsnClass(std::vector &InsnClass, std::map &ComboBitToBitsMap) const { for (std::set::const_iterator SI = stateInfo.begin(); SI != stateInfo.end(); ++SI) { - // Check to see if all required resources are available. bool available = true; @@ -514,8 +517,7 @@ const State &DFA::newState() { int State::currentStateNum = 0; DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R): - TargetName(CodeGenTarget(R).getName()), - allInsnClasses(), Records(R) {} + TargetName(CodeGenTarget(R).getName()), Records(R) {} // // writeTableAndAPI - Print out a table representing the DFA and the @@ -531,7 +533,6 @@ DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R): void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName, int numInsnClasses, int maxResources, int numCombos, int maxStages) { - unsigned numStates = states.size(); DEBUG(dbgs() << "-----------------------------------------------------------------------------\n"); @@ -783,7 +784,7 @@ int DFAPacketizerEmitter::collectOneInsnClass(const std::string &ProcName, DEBUG(dbgs() << " (bits: 0x" << utohexstr(UnitBitValue) << ")\n"); } - if (UnitBits.size() > 0) + if (!UnitBits.empty()) allInsnClasses.push_back(UnitBits); DEBUG({ @@ -831,7 +832,6 @@ int DFAPacketizerEmitter::collectAllInsnClasses(const std::string &ProcName, // Run the worklist algorithm to generate the DFA. // void DFAPacketizerEmitter::run(raw_ostream &OS) { - // Collect processor iteraries. std::vector ProcItinList = Records.getAllDerivedDefinitions("ProcessorItineraries"); @@ -890,7 +890,6 @@ void DFAPacketizerEmitter::run(raw_ostream &OS) { Initial->isInitial = true; Initial->stateInfo.insert(0x0); SmallVector WorkList; -// std::queue WorkList; std::map, const State*> Visited; WorkList.push_back(Initial); @@ -937,7 +936,7 @@ void DFAPacketizerEmitter::run(raw_ostream &OS) { current->canMaybeAddInsnClass(InsnClass, ComboBitToBitsMap)) { const State *NewState = nullptr; current->AddInsnClass(InsnClass, ComboBitToBitsMap, NewStateResources); - if (NewStateResources.size() == 0) { + if (NewStateResources.empty()) { DEBUG(dbgs() << " Skipped - no new states generated\n"); continue; } @@ -989,4 +988,4 @@ void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) { DFAPacketizerEmitter(RK).run(OS); } -} // end namespaec llvm +} // end namespace llvm diff --git a/utils/TableGen/FixedLenDecoderEmitter.cpp b/utils/TableGen/FixedLenDecoderEmitter.cpp index f2d54e6fe5a..a20b469cd84 100644 --- a/utils/TableGen/FixedLenDecoderEmitter.cpp +++ b/utils/TableGen/FixedLenDecoderEmitter.cpp @@ -12,22 +12,32 @@ // //===----------------------------------------------------------------------===// +#include "CodeGenInstruction.h" #include "CodeGenTarget.h" #include "llvm/ADT/APInt.h" +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/CachedHashString.h" #include "llvm/ADT/SmallString.h" +#include "llvm/ADT/SetVector.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" -#include "llvm/ADT/Twine.h" #include "llvm/MC/MCFixedLenDisassembler.h" -#include "llvm/Support/DataTypes.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/LEB128.h" #include "llvm/Support/raw_ostream.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" +#include +#include +#include +#include #include +#include +#include #include #include #include @@ -37,6 +47,7 @@ using namespace llvm; #define DEBUG_TYPE "decoder-emitter" namespace { + struct EncodingField { unsigned Base, Width, Offset; EncodingField(unsigned B, unsigned W, unsigned O) @@ -76,13 +87,10 @@ struct DecoderTableInfo { DecoderSet Decoders; }; -} // End anonymous namespace - -namespace { class FixedLenDecoderEmitter { ArrayRef NumberedInstructions; -public: +public: // Defaults preserved here for documentation, even though they aren't // strictly necessary given the way that this is currently being called. FixedLenDecoderEmitter(RecordKeeper &R, std::string PredicateNamespace, @@ -112,13 +120,15 @@ public: private: CodeGenTarget Target; + public: std::string PredicateNamespace; std::string GuardPrefix, GuardPostfix; std::string ReturnOK, ReturnFail; std::string Locals; }; -} // End anonymous namespace + +} // end anonymous namespace // The set (BIT_TRUE, BIT_FALSE, BIT_UNSET) represents a ternary logic system // for a bit value. @@ -135,12 +145,15 @@ typedef enum { static bool ValueSet(bit_value_t V) { return (V == BIT_TRUE || V == BIT_FALSE); } + static bool ValueNotSet(bit_value_t V) { return (V == BIT_UNSET); } + static int Value(bit_value_t V) { return ValueNotSet(V) ? -1 : (V == BIT_FALSE ? 0 : 1); } + static bit_value_t bitFromBits(const BitsInit &bits, unsigned index) { if (BitInit *bit = dyn_cast(bits.getBit(index))) return bit->getValue() ? BIT_TRUE : BIT_FALSE; @@ -148,6 +161,7 @@ static bit_value_t bitFromBits(const BitsInit &bits, unsigned index) { // The bit is uninitialized. return BIT_UNSET; } + // Prints the bit value for each position. static void dumpBits(raw_ostream &o, const BitsInit &bits) { for (unsigned index = bits.getNumBits(); index > 0; --index) { @@ -172,14 +186,13 @@ static BitsInit &getBitsField(const Record &def, StringRef str) { return *bits; } -// Forward declaration. -namespace { -class FilterChooser; -} // End anonymous namespace - // Representation of the instruction to work on. typedef std::vector insn_t; +namespace { + +class FilterChooser; + /// Filter - Filter works with FilterChooser to produce the decoding tree for /// the ISA. /// @@ -216,7 +229,6 @@ typedef std::vector insn_t; /// decoder could try to decode the even/odd register numbering and assign to /// VST4q8a or VST4q8b, but for the time being, the decoder chooses the "a" /// version and return the Opcode since the two have the same Asm format string. -namespace { class Filter { protected: const FilterChooser *Owner;// points to the FilterChooser who owns this filter @@ -225,7 +237,7 @@ protected: bool Mixed; // a mixed region contains both set and unset bits // Map of well-known segment value to the set of uid's with that value. - std::map > FilteredInstructions; + std::map> FilteredInstructions; // Set of uid's with non-constant segment values. std::vector VariableInstructions; @@ -240,11 +252,18 @@ protected: unsigned LastOpcFiltered; public: + Filter(Filter &&f); + Filter(FilterChooser &owner, unsigned startBit, unsigned numBits, bool mixed); + + ~Filter() = default; + unsigned getNumFiltered() const { return NumFiltered; } + unsigned getSingletonOpc() const { assert(NumFiltered == 1); return LastOpcFiltered; } + // Return the filter chooser for the group of instructions without constant // segment values. const FilterChooser &getVariableFC() const { @@ -253,11 +272,6 @@ public: return *(FilterChooserMap.find((unsigned)-1)->second); } - Filter(Filter &&f); - Filter(FilterChooser &owner, unsigned startBit, unsigned numBits, bool mixed); - - ~Filter(); - // Divides the decoding task into sub tasks and delegates them to the // inferior FilterChooser's. // @@ -273,8 +287,9 @@ public: // Returns the number of fanout produced by the filter. More fanout implies // the filter distinguishes more categories of instructions. unsigned usefulness() const; -}; // End of class Filter -} // End anonymous namespace +}; // end class Filter + +} // end anonymous namespace // These are states of our finite state machines used in FilterChooser's // filterProcessor() which produces the filter candidates to use. @@ -302,6 +317,7 @@ typedef enum { /// decoding tree. And each case is delegated to an inferior FilterChooser to /// decide what further remaining bits to look at. namespace { + class FilterChooser { protected: friend class Filter; @@ -313,7 +329,7 @@ protected: const std::vector &Opcodes; // Lookup table for the operand decoding of instructions. - const std::map > &Operands; + const std::map> &Operands; // Vector of candidate filters. std::vector Filters; @@ -334,16 +350,13 @@ protected: // Parent emitter const FixedLenDecoderEmitter *Emitter; - FilterChooser(const FilterChooser &) = delete; - void operator=(const FilterChooser &) = delete; public: - FilterChooser(ArrayRef Insts, const std::vector &IDs, - const std::map > &Ops, + const std::map> &Ops, unsigned BW, const FixedLenDecoderEmitter *E) - : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(), + : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), FilterBitValues(BW, BIT_UNFILTERED), Parent(nullptr), BestIndex(-1), BitWidth(BW), Emitter(E) { doFilter(); @@ -351,16 +364,18 @@ public: FilterChooser(ArrayRef Insts, const std::vector &IDs, - const std::map > &Ops, + const std::map> &Ops, const std::vector &ParentFilterBitValues, const FilterChooser &parent) : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), - Filters(), FilterBitValues(ParentFilterBitValues), - Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth), - Emitter(parent.Emitter) { + FilterBitValues(ParentFilterBitValues), Parent(&parent), BestIndex(-1), + BitWidth(parent.BitWidth), Emitter(parent.Emitter) { doFilter(); } + FilterChooser(const FilterChooser &) = delete; + void operator=(const FilterChooser &) = delete; + unsigned getBitWidth() const { return BitWidth; } protected: @@ -477,7 +492,8 @@ public: // instructions. void emitTableEntries(DecoderTableInfo &TableInfo) const; }; -} // End anonymous namespace + +} // end anonymous namespace /////////////////////////// // // @@ -528,9 +544,6 @@ Filter::Filter(FilterChooser &owner, unsigned startBit, unsigned numBits, && "Filter returns no instruction categories"); } -Filter::~Filter() { -} - // Divides the decoding task into sub tasks and delegates them to the // inferior FilterChooser's. // @@ -1072,7 +1085,7 @@ void FilterChooser::emitDecoder(raw_ostream &OS, unsigned Indentation, for (const auto &Op : Operands.find(Opc)->second) { // If a custom instruction decoder was specified, use that. - if (Op.numFields() == 0 && Op.Decoder.size()) { + if (Op.numFields() == 0 && !Op.Decoder.empty()) { HasCompleteDecoder = Op.HasCompleteDecoder; OS.indent(Indentation) << Emitter->GuardPrefix << Op.Decoder << "(MI, insn, Address, Decoder)" @@ -1142,7 +1155,7 @@ bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation, StringRef SR(P); std::pair pairs = SR.split(','); - while (pairs.second.size()) { + while (!pairs.second.empty()) { emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace); o << " && "; pairs = pairs.second.split(','); @@ -1371,7 +1384,6 @@ void FilterChooser::emitSingletonTableEntry(DecoderTableInfo &TableInfo, Best.getVariableFC().emitTableEntries(TableInfo); } - // Assign a single filter and run with it. Top level API client can initialize // with a single filter to start the filtering process. void FilterChooser::runSingleFilter(unsigned startBit, unsigned numBit, @@ -1719,7 +1731,7 @@ static std::string findOperandDecoderMethod(TypedInit *TI) { static bool populateInstruction(CodeGenTarget &Target, const CodeGenInstruction &CGI, unsigned Opc, - std::map > &Operands){ + std::map> &Operands){ const Record &Def = *CGI.TheDef; // If all the bit positions are not specified; do not decode this instruction. // We are bound to fail! For proper disassembly, the well-known encoding bits @@ -1747,7 +1759,7 @@ static bool populateInstruction(CodeGenTarget &Target, // Gather the outputs/inputs of the instruction, so we can find their // positions in the encoding. This assumes for now that they appear in the // MCInst in the order that they're listed. - std::vector > InOutOperands; + std::vector> InOutOperands; DagInit *Out = Def.getValueAsDag("OutOperandList"); DagInit *In = Def.getValueAsDag("InOperandList"); for (unsigned i = 0; i < Out->getNumArgs(); ++i) @@ -1768,7 +1780,7 @@ static bool populateInstruction(CodeGenTarget &Target, } } - std::map > NumberedInsnOperands; + std::map> NumberedInsnOperands; std::set NumberedInsnOperandsNoTie; if (Target.getInstructionSet()-> getValueAsBit("decodePositionallyEncodedOperands")) { @@ -1853,7 +1865,7 @@ static bool populateInstruction(CodeGenTarget &Target, Name << "(" << SO.first << ", " << SO.second << ") => " << Vals[i].getName() << "\n"); - std::string Decoder = ""; + std::string Decoder; Record *TypeRecord = CGI.Operands[SO.first].Rec; RecordVal *DecoderString = TypeRecord->getValue("DecoderMethod"); @@ -2014,7 +2026,6 @@ static bool populateInstruction(CodeGenTarget &Target, Operands[Opc] = InsnOperands; - #if 0 DEBUG({ // Dumps the instruction encoding bits. @@ -2067,7 +2078,7 @@ static void emitDecodeInstruction(formatted_raw_ostream &OS) { << " const uint8_t *Ptr = DecodeTable;\n" << " uint32_t CurFieldValue = 0;\n" << " DecodeStatus S = MCDisassembler::Success;\n" - << " for (;;) {\n" + << " while (true) {\n" << " ptrdiff_t Loc = Ptr - DecodeTable;\n" << " switch (*Ptr) {\n" << " default:\n" @@ -2235,8 +2246,8 @@ void FixedLenDecoderEmitter::run(raw_ostream &o) { // Parameterize the decoders based on namespace and instruction width. NumberedInstructions = Target.getInstructionsByEnumValue(); std::map, - std::vector > OpcMap; - std::map > Operands; + std::vector> OpcMap; + std::map> Operands; for (unsigned i = 0; i < NumberedInstructions.size(); ++i) { const CodeGenInstruction *Inst = NumberedInstructions[i]; @@ -2309,4 +2320,4 @@ void EmitFixedLenDecoder(RecordKeeper &RK, raw_ostream &OS, ROK, RFail, L).run(OS); } -} // End llvm namespace +} // end namespace llvm -- 2.50.1