From bf5716cbd7d9558eb298a3f07a1aa2ec7a4bc1db Mon Sep 17 00:00:00 2001 From: Peter Johnson Date: Tue, 22 Apr 2008 05:41:11 +0000 Subject: [PATCH] Fix register fields on FMA instructions. The FMA instructions swap VEX.vvvv and imm8[7:4] as compared to other AVX instructions. Reported by: nasm64developer@users.sf.net svn path=/trunk/yasm/; revision=2071 --- modules/arch/x86/gen_x86_insn.py | 22 +- modules/arch/x86/tests/fma.hex | 360 +++++++++++++++---------------- 2 files changed, 191 insertions(+), 191 deletions(-) diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py index ef19a408..e52ca641 100755 --- a/modules/arch/x86/gen_x86_insn.py +++ b/modules/arch/x86/gen_x86_insn.py @@ -6374,9 +6374,9 @@ add_group("fma_128_256", prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=128, dest="Spare"), - Operand(type="SIMDReg", size=128, dest="VEX"), + Operand(type="SIMDReg", size=128, dest="VEXImmSrc"), Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"), - Operand(type="SIMDReg", size=128, dest="VEXImmSrc")]) + Operand(type="SIMDReg", size=128, dest="VEX")]) add_group("fma_128_256", cpu=["FMA"], modifiers=["Op2Add"], @@ -6385,8 +6385,8 @@ add_group("fma_128_256", prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=128, dest="Spare"), - Operand(type="SIMDReg", size=128, dest="VEX"), Operand(type="SIMDReg", size=128, dest="VEXImmSrc"), + Operand(type="SIMDReg", size=128, dest="VEX"), Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")]) add_group("fma_128_256", cpu=["FMA"], @@ -6396,9 +6396,9 @@ add_group("fma_128_256", prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=256, dest="Spare"), - Operand(type="SIMDReg", size=256, dest="VEX"), + Operand(type="SIMDReg", size=256, dest="VEXImmSrc"), Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"), - Operand(type="SIMDReg", size=256, dest="VEXImmSrc")]) + Operand(type="SIMDReg", size=256, dest="VEX")]) add_group("fma_128_256", cpu=["FMA"], modifiers=["Op2Add"], @@ -6407,8 +6407,8 @@ add_group("fma_128_256", prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=256, dest="Spare"), - Operand(type="SIMDReg", size=256, dest="VEX"), Operand(type="SIMDReg", size=256, dest="VEXImmSrc"), + Operand(type="SIMDReg", size=256, dest="VEX"), Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")]) add_insn("vfmaddpd", "fma_128_256", modifiers=[0x69]) @@ -6433,9 +6433,9 @@ for sz in [32, 64]: prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=128, dest="Spare"), - Operand(type="SIMDReg", size=128, dest="VEX"), + Operand(type="SIMDReg", size=128, dest="VEXImmSrc"), Operand(type="SIMDReg", size=128, dest="EA"), - Operand(type="SIMDReg", size=128, dest="VEXImmSrc")]) + Operand(type="SIMDReg", size=128, dest="VEX")]) add_group("fma_128_m%d" % sz, cpu=["FMA"], modifiers=["Op2Add"], @@ -6444,9 +6444,9 @@ for sz in [32, 64]: prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=128, dest="Spare"), - Operand(type="SIMDReg", size=128, dest="VEX"), + Operand(type="SIMDReg", size=128, dest="VEXImmSrc"), Operand(type="Mem", size=sz, relaxed=True, dest="EA"), - Operand(type="SIMDReg", size=128, dest="VEXImmSrc")]) + Operand(type="SIMDReg", size=128, dest="VEX")]) add_group("fma_128_m%d" % sz, cpu=["FMA"], modifiers=["Op2Add"], @@ -6455,8 +6455,8 @@ for sz in [32, 64]: prefix=0x66, opcode=[0x0F, 0x3A, 0x00], operands=[Operand(type="SIMDReg", size=128, dest="Spare"), - Operand(type="SIMDReg", size=128, dest="VEX"), Operand(type="SIMDReg", size=128, dest="VEXImmSrc"), + Operand(type="SIMDReg", size=128, dest="VEX"), Operand(type="Mem", size=sz, relaxed=True, dest="EA")]) add_insn("vfmaddsd", "fma_128_m64", modifiers=[0x6B]) diff --git a/modules/arch/x86/tests/fma.hex b/modules/arch/x86/tests/fma.hex index a1193179..7f51092a 100644 --- a/modules/arch/x86/tests/fma.hex +++ b/modules/arch/x86/tests/fma.hex @@ -1,540 +1,540 @@ c4 e3 -71 +61 69 c2 -30 +10 c4 e3 -71 +61 69 00 -30 +10 c4 e3 -71 +61 69 00 -30 +10 c4 e3 -f1 +e9 69 00 -20 +10 c4 e3 -f1 +e9 69 00 -20 +10 c4 e3 -75 +65 69 c2 -30 +10 c4 e3 -75 +65 69 00 -30 +10 c4 e3 -75 +65 69 00 -30 +10 c4 e3 -f5 +ed 69 00 -20 +10 c4 e3 -f5 +ed 69 00 -20 +10 c4 e3 -71 +61 68 c2 -30 +10 c4 e3 -71 +61 68 00 -30 +10 c4 e3 -f1 +e9 68 00 -20 +10 c4 e3 -75 +65 68 c2 -30 +10 c4 e3 -75 +65 68 00 -30 +10 c4 e3 -f5 +ed 68 00 -20 +10 c4 e3 -71 +61 6b c2 -30 +10 c4 e3 -71 +61 6b 00 -30 +10 c4 e3 -71 +61 6b 00 -30 +10 c4 e3 -f1 +e9 6b 00 -20 +10 c4 e3 -f1 +e9 6b 00 -20 +10 c4 e3 -71 +61 6a c2 -30 +10 c4 e3 -71 +61 6a 00 -30 +10 c4 e3 -f1 +e9 6a 00 -20 +10 c4 e3 -71 +61 5d c2 -30 +10 c4 e3 -71 +61 5d 00 -30 +10 c4 e3 -f1 +e9 5d 00 -20 +10 c4 e3 -75 +65 5d c2 -30 +10 c4 e3 -75 +65 5d 00 -30 +10 c4 e3 -f5 +ed 5d 00 -20 +10 c4 e3 -71 +61 5c c2 -30 +10 c4 e3 -71 +61 5c 00 -30 +10 c4 e3 -f1 +e9 5c 00 -20 +10 c4 e3 -75 +65 5c c2 -30 +10 c4 e3 -75 +65 5c 00 -30 +10 c4 e3 -f5 +ed 5c 00 -20 +10 c4 e3 -71 +61 6d c2 -30 +10 c4 e3 -71 +61 6d 00 -30 +10 c4 e3 -f1 +e9 6d 00 -20 +10 c4 e3 -75 +65 6d c2 -30 +10 c4 e3 -75 +65 6d 00 -30 +10 c4 e3 -f5 +ed 6d 00 -20 +10 c4 e3 -71 +61 6c c2 -30 +10 c4 e3 -71 +61 6c 00 -30 +10 c4 e3 -f1 +e9 6c 00 -20 +10 c4 e3 -75 +65 6c c2 -30 +10 c4 e3 -75 +65 6c 00 -30 +10 c4 e3 -f5 +ed 6c 00 -20 +10 c4 e3 -71 +61 6f c2 -30 +10 c4 e3 -71 +61 6f 00 -30 +10 c4 e3 -f1 +e9 6f 00 -20 +10 c4 e3 -71 +61 6e c2 -30 +10 c4 e3 -71 +61 6e 00 -30 +10 c4 e3 -f1 +e9 6e 00 -20 +10 c4 e3 -71 +61 79 c2 -30 +10 c4 e3 -71 +61 79 00 -30 +10 c4 e3 -f1 +e9 79 00 -20 +10 c4 e3 -75 +65 79 c2 -30 +10 c4 e3 -75 +65 79 00 -30 +10 c4 e3 -f5 +ed 79 00 -20 +10 c4 e3 -71 +61 78 c2 -30 +10 c4 e3 -71 +61 78 00 -30 +10 c4 e3 -f1 +e9 78 00 -20 +10 c4 e3 -75 +65 78 c2 -30 +10 c4 e3 -75 +65 78 00 -30 +10 c4 e3 -f5 +ed 78 00 -20 +10 c4 e3 -71 +61 7b c2 -30 +10 c4 e3 -71 +61 7b 00 -30 +10 c4 e3 -f1 +e9 7b 00 -20 +10 c4 e3 -71 +61 7a c2 -30 +10 c4 e3 -71 +61 7a 00 -30 +10 c4 e3 -f1 +e9 7a 00 -20 +10 c4 e3 -71 +61 7d c2 -30 +10 c4 e3 -71 +61 7d 00 -30 +10 c4 e3 -f1 +e9 7d 00 -20 +10 c4 e3 -75 +65 7d c2 -30 +10 c4 e3 -75 +65 7d 00 -30 +10 c4 e3 -f5 +ed 7d 00 -20 +10 c4 e3 -71 +61 7c c2 -30 +10 c4 e3 -71 +61 7c 00 -30 +10 c4 e3 -f1 +e9 7c 00 -20 +10 c4 e3 -75 +65 7c c2 -30 +10 c4 e3 -75 +65 7c 00 -30 +10 c4 e3 -f5 +ed 7c 00 -20 +10 c4 e3 -71 +61 7f c2 -30 +10 c4 e3 -71 +61 7f 00 -30 +10 c4 e3 -f1 +e9 7f 00 -20 +10 c4 e3 -71 +61 7e c2 -30 +10 c4 e3 -71 +61 7e 00 -30 +10 c4 e3 -f1 +e9 7e 00 -20 +10 -- 2.49.0