From be849ca61f09d3c048ca39146df12f144d68264a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 19 Feb 2019 17:16:23 +0000 Subject: [PATCH] [X86] Bugfix for nullptr check by klocwork klocwork critical issues in CG files: Patch by Xiang Zhang (xiangzhangllvm) Differential Revision: https://reviews.llvm.org/D58363 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354357 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86DiscriminateMemOps.cpp | 3 ++- lib/Target/X86/X86InstructionSelector.cpp | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/lib/Target/X86/X86DiscriminateMemOps.cpp b/lib/Target/X86/X86DiscriminateMemOps.cpp index f6bd5804261..22271896f6c 100644 --- a/lib/Target/X86/X86DiscriminateMemOps.cpp +++ b/lib/Target/X86/X86DiscriminateMemOps.cpp @@ -85,7 +85,7 @@ bool X86DiscriminateMemOps::runOnMachineFunction(MachineFunction &MF) { // have any debug info. const DILocation *ReferenceDI = DILocation::get(FDI->getContext(), FDI->getLine(), 0, FDI); - + assert(ReferenceDI && "ReferenceDI should not be nullptr"); DenseMap MemOpDiscriminators; MemOpDiscriminators[diToLocation(ReferenceDI)] = 0; @@ -143,6 +143,7 @@ bool X86DiscriminateMemOps::runOnMachineFunction(MachineFunction &MF) { // Since we were able to encode, bump the MemOpDiscriminators. ++MemOpDiscriminators[L]; DI = DI->cloneWithDiscriminator(EncodedDiscriminator.getValue()); + assert(DI && "DI should not be nullptr"); updateDebugInfo(&MI, DI); Changed = true; std::pair::iterator, bool> MustInsert = diff --git a/lib/Target/X86/X86InstructionSelector.cpp b/lib/Target/X86/X86InstructionSelector.cpp index 0fdd6e379b4..cd2e9b82a6f 100644 --- a/lib/Target/X86/X86InstructionSelector.cpp +++ b/lib/Target/X86/X86InstructionSelector.cpp @@ -1600,8 +1600,8 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I, assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && "Arguments and return value types must match"); - const RegisterBank &RegRB = *RBI.getRegBank(DstReg, MRI, TRI); - if (RegRB.getID() != X86::GPRRegBankID) + const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI); + if (!RegRB || RegRB->getID() != X86::GPRRegBankID) return false; const static unsigned NumTypes = 4; // i8, i16, i32, i64 @@ -1699,7 +1699,7 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I, const DivRemEntry &TypeEntry = *OpEntryIt; const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; - const TargetRegisterClass *RegRC = getRegClass(RegTy, RegRB); + const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB); if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) || !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) || !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) { -- 2.50.1