From b9eb67aedbf7daa571d9fcbea19752f6f3d3ce63 Mon Sep 17 00:00:00 2001 From: Luis Marques Date: Tue, 26 Mar 2019 15:41:45 +0000 Subject: [PATCH] [RISCV] Update setcc-logic.ll codegen test This should have been updated as part of D59753. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357002 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/RISCV/setcc-logic.ll | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/test/CodeGen/RISCV/setcc-logic.ll b/test/CodeGen/RISCV/setcc-logic.ll index 2303e556346..72f797db15a 100644 --- a/test/CodeGen/RISCV/setcc-logic.ll +++ b/test/CodeGen/RISCV/setcc-logic.ll @@ -102,26 +102,22 @@ define i1 @and_icmps_const_1bit_diff(i32 %x) nounwind { define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind { ; RV32I-LABEL: and_icmps_const_not1bit_diff: ; RV32I: # %bb.0: -; RV32I-NEXT: addi a1, zero, 44 -; RV32I-NEXT: xor a1, a0, a1 -; RV32I-NEXT: addi a2, zero, 92 -; RV32I-NEXT: xor a0, a0, a2 -; RV32I-NEXT: snez a0, a0 +; RV32I-NEXT: xori a1, a0, 92 ; RV32I-NEXT: snez a1, a1 -; RV32I-NEXT: and a0, a1, a0 +; RV32I-NEXT: xori a0, a0, 44 +; RV32I-NEXT: snez a0, a0 +; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: and_icmps_const_not1bit_diff: ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 -; RV64I-NEXT: addi a1, zero, 44 -; RV64I-NEXT: xor a1, a0, a1 -; RV64I-NEXT: addi a2, zero, 92 -; RV64I-NEXT: xor a0, a0, a2 -; RV64I-NEXT: snez a0, a0 +; RV64I-NEXT: xori a1, a0, 92 ; RV64I-NEXT: snez a1, a1 -; RV64I-NEXT: and a0, a1, a0 +; RV64I-NEXT: xori a0, a0, 44 +; RV64I-NEXT: snez a0, a0 +; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret %a = icmp ne i32 %x, 44 %b = icmp ne i32 %x, 92 -- 2.40.0