From b9253653c7143ba510d892be2b30e1b8c11affe6 Mon Sep 17 00:00:00 2001 From: Joerg Sonnenberger Date: Tue, 29 Jul 2014 22:21:57 +0000 Subject: [PATCH] Support move to/from segment register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214234 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 1 + .../PowerPC/InstPrinter/PPCInstPrinter.cpp | 7 ++++++ .../PowerPC/InstPrinter/PPCInstPrinter.h | 1 + lib/Target/PowerPC/PPCInstrFormats.td | 22 +++++++++++++++++++ lib/Target/PowerPC/PPCInstrInfo.td | 21 ++++++++++++++++++ .../Disassembler/PowerPC/ppc64-encoding.txt | 4 ++++ test/MC/PowerPC/ppc64-encoding.s | 14 ++++++++++++ 7 files changed, 70 insertions(+) diff --git a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index d7066d58709..a3ba00d7a83 100644 --- a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -409,6 +409,7 @@ public: bool isToken() const override { return Kind == Token; } bool isImm() const override { return Kind == Immediate || Kind == Expression; } bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } + bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } diff --git a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp index 771b6f5ec48..35ba3c008f2 100644 --- a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp +++ b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp @@ -208,6 +208,13 @@ void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo, O << (unsigned int)Value; } +void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + unsigned int Value = MI->getOperand(OpNo).getImm(); + assert(Value <= 15 && "Invalid u4imm argument!"); + O << (unsigned int)Value; +} + void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { int Value = MI->getOperand(OpNo).getImm(); diff --git a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h index 211a62813e7..77bf980bc92 100644 --- a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h +++ b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h @@ -44,6 +44,7 @@ public: raw_ostream &O, const char *Modifier = nullptr); void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 1e4396cd101..c95aefafab0 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -457,6 +457,28 @@ class XForm_16 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, let Inst{31} = 0; } +class XForm_sr opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : I { + bits<5> RS; + bits<4> SR; + + let Inst{6-10} = RS; + let Inst{12-15} = SR; + let Inst{21-30} = xo; +} + +class XForm_srin opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : I { + bits<5> RS; + bits<5> RB; + + let Inst{6-10} = RS; + let Inst{16-20} = RB; + let Inst{21-30} = xo; +} + class XForm_mtmsr opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> : I { diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 0596c15ea37..dbaf8f3ed52 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -420,6 +420,15 @@ def u2imm : Operand { let PrintMethod = "printU2ImmOperand"; let ParserMatchClass = PPCU2ImmAsmOperand; } + +def PPCU4ImmAsmOperand : AsmOperandClass { + let Name = "U4Imm"; let PredicateMethod = "isU4Imm"; + let RenderMethod = "addImmOperands"; +} +def u4imm : Operand { + let PrintMethod = "printU4ImmOperand"; + let ParserMatchClass = PPCU4ImmAsmOperand; +} def PPCS5ImmAsmOperand : AsmOperandClass { let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; let RenderMethod = "addImmOperands"; @@ -3037,6 +3046,18 @@ def EIEIO : XForm_24_eieio<31, 854, (outs), (ins), def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L), "wait $L", IIC_LdStLoad, []>; +def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), + "mtsr $SR, $RS", IIC_SprMTSR>; + +def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), + "mfsr $RS, $SR", IIC_SprMFSR>; + +def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), + "mtsrin $RS, $RB", IIC_SprMTSR>; + +def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), + "mfsrin $RS, $RB", IIC_SprMFSR>; + def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L), "mtmsr $RS, $L", IIC_SprMTMSR>; diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding.txt index 33a8c0ed5de..2e2e7c1e650 100644 --- a/test/MC/Disassembler/PowerPC/ppc64-encoding.txt +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding.txt @@ -619,3 +619,7 @@ # CHECK: mfocrf 16, 8 0x7e 0x10 0x80 0x26 +# CHECK: mtsrin 10, 12 +0x7d 0x40 0x61 0xe4 +# CHECK: mfsrin 10, 12 +0x7d 0x40 0x65 0x26 diff --git a/test/MC/PowerPC/ppc64-encoding.s b/test/MC/PowerPC/ppc64-encoding.s index 4c3530d9c62..d483f9df6fe 100644 --- a/test/MC/PowerPC/ppc64-encoding.s +++ b/test/MC/PowerPC/ppc64-encoding.s @@ -767,3 +767,17 @@ # CHECK-LE: mfocrf 16, 8 # encoding: [0x26,0x80,0x10,0x7e] mfocrf 16, 8 +# Move to/from segment register +# CHECK-BE: mtsr 12, 10 # encoding: [0x7d,0x4c,0x01,0xa4] +# CHECK-LE: mtsr 12, 10 # encoding: [0xa4,0x01,0x4c,0x7d] + mtsr 12,%r10 +# CHECK-BE: mfsr 10, 12 # encoding: [0x7d,0x4c,0x04,0xa6] +# CHECK-LE: mfsr 10, 12 # encoding: [0xa6,0x04,0x4c,0x7d] + mfsr %r10,12 + +# CHECK-BE: mtsrin 10, 12 # encoding: [0x7d,0x40,0x61,0xe4] +# CHECK-LE: mtsrin 10, 12 # encoding: [0xe4,0x61,0x40,0x7d] + mtsrin %r10,%r12 +# CHECK-BE: mfsrin 10, 12 # encoding: [0x7d,0x40,0x65,0x26] +# CHECK-LE: mfsrin 10, 12 # encoding: [0x26,0x65,0x40,0x7d] + mfsrin %r10,%r12 -- 2.40.0