From b75805f86228651cca0431c5d9e9a6b248bf9519 Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Tue, 15 Oct 2019 12:56:24 +0000 Subject: [PATCH] [Alignment] Migrate Attribute::getWith(Stack)Alignment Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet, jdoerfert Reviewed By: courbet Subscribers: arsenm, jvesely, nhaehnle, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D68792 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374884 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IR/Attributes.h | 4 ++-- include/llvm/IR/IntrinsicInst.h | 17 ++++++++-------- lib/IR/Attributes.cpp | 19 ++++++++---------- lib/IR/Core.cpp | 5 +++-- lib/IR/IRBuilder.cpp | 6 ++++-- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 9 ++++----- .../AMDGPU/AMDGPUHSAMetadataStreamer.cpp | 9 +++++---- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 2 +- .../AMDGPU/AMDGPULowerKernelArguments.cpp | 20 +++++++++---------- lib/Target/AMDGPU/AMDGPUMachineFunction.cpp | 1 - lib/Target/AMDGPU/AMDGPUMachineFunction.h | 6 ++---- lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 14 ++++++------- lib/Target/AMDGPU/AMDGPUSubtarget.h | 10 ++++------ lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 +- lib/Transforms/IPO/Attributor.cpp | 3 ++- .../AMDGPU/machine-function-info-no-ir.mir | 9 ++++++--- .../MIR/AMDGPU/machine-function-info.ll | 6 +++--- unittests/IR/AttributesTest.cpp | 8 ++++---- 18 files changed, 75 insertions(+), 75 deletions(-) diff --git a/include/llvm/IR/Attributes.h b/include/llvm/IR/Attributes.h index 719b9992cce..6436ee05aa7 100644 --- a/include/llvm/IR/Attributes.h +++ b/include/llvm/IR/Attributes.h @@ -95,8 +95,8 @@ public: /// Return a uniquified Attribute object that has the specific /// alignment set. - static Attribute getWithAlignment(LLVMContext &Context, uint64_t Align); - static Attribute getWithStackAlignment(LLVMContext &Context, uint64_t Align); + static Attribute getWithAlignment(LLVMContext &Context, Align Alignment); + static Attribute getWithStackAlignment(LLVMContext &Context, Align Alignment); static Attribute getWithDereferenceableBytes(LLVMContext &Context, uint64_t Bytes); static Attribute getWithDereferenceableOrNullBytes(LLVMContext &Context, diff --git a/include/llvm/IR/IntrinsicInst.h b/include/llvm/IR/IntrinsicInst.h index 9400f0a0801..c989b4a2e72 100644 --- a/include/llvm/IR/IntrinsicInst.h +++ b/include/llvm/IR/IntrinsicInst.h @@ -411,11 +411,11 @@ namespace llvm { setArgOperand(ARG_DEST, Ptr); } - void setDestAlignment(unsigned Align) { + void setDestAlignment(unsigned Alignment) { removeParamAttr(ARG_DEST, Attribute::Alignment); - if (Align > 0) - addParamAttr(ARG_DEST, - Attribute::getWithAlignment(getContext(), Align)); + if (Alignment > 0) + addParamAttr(ARG_DEST, Attribute::getWithAlignment(getContext(), + Align(Alignment))); } void setLength(Value *L) { @@ -460,11 +460,12 @@ namespace llvm { BaseCL::setArgOperand(ARG_SOURCE, Ptr); } - void setSourceAlignment(unsigned Align) { + void setSourceAlignment(unsigned Alignment) { BaseCL::removeParamAttr(ARG_SOURCE, Attribute::Alignment); - if (Align > 0) - BaseCL::addParamAttr(ARG_SOURCE, Attribute::getWithAlignment( - BaseCL::getContext(), Align)); + if (Alignment > 0) + BaseCL::addParamAttr(ARG_SOURCE, + Attribute::getWithAlignment(BaseCL::getContext(), + Align(Alignment))); } }; diff --git a/lib/IR/Attributes.cpp b/lib/IR/Attributes.cpp index a68ad50cf2c..dda70f4dc59 100644 --- a/lib/IR/Attributes.cpp +++ b/lib/IR/Attributes.cpp @@ -142,17 +142,14 @@ Attribute Attribute::get(LLVMContext &Context, Attribute::AttrKind Kind, return Attribute(PA); } -Attribute Attribute::getWithAlignment(LLVMContext &Context, uint64_t Align) { - assert(isPowerOf2_32(Align) && "Alignment must be a power of two."); - assert(Align <= 0x40000000 && "Alignment too large."); - return get(Context, Alignment, Align); +Attribute Attribute::getWithAlignment(LLVMContext &Context, Align A) { + assert(A <= 0x40000000 && "Alignment too large."); + return get(Context, Alignment, A.value()); } -Attribute Attribute::getWithStackAlignment(LLVMContext &Context, - uint64_t Align) { - assert(isPowerOf2_32(Align) && "Alignment must be a power of two."); - assert(Align <= 0x100 && "Alignment too large."); - return get(Context, StackAlignment, Align); +Attribute Attribute::getWithStackAlignment(LLVMContext &Context, Align A) { + assert(A <= 0x100 && "Alignment too large."); + return get(Context, StackAlignment, A.value()); } Attribute Attribute::getWithDereferenceableBytes(LLVMContext &Context, @@ -782,10 +779,10 @@ AttributeSetNode *AttributeSetNode::get(LLVMContext &C, const AttrBuilder &B) { Attr = Attribute::getWithByValType(C, B.getByValType()); break; case Attribute::Alignment: - Attr = Attribute::getWithAlignment(C, B.getAlignment()); + Attr = Attribute::getWithAlignment(C, Align(B.getAlignment())); break; case Attribute::StackAlignment: - Attr = Attribute::getWithStackAlignment(C, B.getStackAlignment()); + Attr = Attribute::getWithStackAlignment(C, Align(B.getStackAlignment())); break; case Attribute::Dereferenceable: Attr = Attribute::getWithDereferenceableBytes( diff --git a/lib/IR/Core.cpp b/lib/IR/Core.cpp index afa73b33cd1..a5f46b16e60 100644 --- a/lib/IR/Core.cpp +++ b/lib/IR/Core.cpp @@ -2489,7 +2489,7 @@ LLVMValueRef LLVMGetPreviousParam(LLVMValueRef Arg) { void LLVMSetParamAlignment(LLVMValueRef Arg, unsigned align) { Argument *A = unwrap(Arg); - A->addAttr(Attribute::getWithAlignment(A->getContext(), align)); + A->addAttr(Attribute::getWithAlignment(A->getContext(), Align(align))); } /*--.. Operations on ifuncs ................................................--*/ @@ -2788,7 +2788,8 @@ void LLVMSetInstructionCallConv(LLVMValueRef Instr, unsigned CC) { void LLVMSetInstrParamAlignment(LLVMValueRef Instr, unsigned index, unsigned align) { auto *Call = unwrap(Instr); - Attribute AlignAttr = Attribute::getWithAlignment(Call->getContext(), align); + Attribute AlignAttr = + Attribute::getWithAlignment(Call->getContext(), Align(align)); Call->addAttribute(index, AlignAttr); } diff --git a/lib/IR/IRBuilder.cpp b/lib/IR/IRBuilder.cpp index 933b511b604..b782012e973 100644 --- a/lib/IR/IRBuilder.cpp +++ b/lib/IR/IRBuilder.cpp @@ -289,8 +289,10 @@ CallInst *IRBuilderBase::CreateElementUnorderedAtomicMemMove( CallInst *CI = createCallHelper(TheFn, Ops, this); // Set the alignment of the pointer args. - CI->addParamAttr(0, Attribute::getWithAlignment(CI->getContext(), DstAlign)); - CI->addParamAttr(1, Attribute::getWithAlignment(CI->getContext(), SrcAlign)); + CI->addParamAttr( + 0, Attribute::getWithAlignment(CI->getContext(), Align(DstAlign))); + CI->addParamAttr( + 1, Attribute::getWithAlignment(CI->getContext(), Align(SrcAlign))); // Set the TBAA info if present. if (TBAATag) diff --git a/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index b83cc7f2528..f2d903c8e7b 100644 --- a/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -1261,17 +1261,16 @@ void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out, if (STM.isXNACKEnabled()) Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED; - unsigned MaxKernArgAlign; + Align MaxKernArgAlign; Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign); Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR; Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR; Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize; Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize; - // These alignment values are specified in powers of two, so alignment = - // 2^n. The minimum alignment is 2^4 = 16. - Out.kernarg_segment_alignment = std::max(4, - countTrailingZeros(MaxKernArgAlign)); + // kernarg_segment_alignment is specified as log of the alignment. + // The minimum alignment is 16. + Out.kernarg_segment_alignment = Log2(std::max(Align(16), MaxKernArgAlign)); } bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, diff --git a/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp b/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp index b31de0af501..9f5bcd8ff5f 100644 --- a/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp +++ b/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp @@ -218,12 +218,13 @@ MetadataStreamerV2::getHSACodeProps(const MachineFunction &MF, assert(F.getCallingConv() == CallingConv::AMDGPU_KERNEL || F.getCallingConv() == CallingConv::SPIR_KERNEL); - unsigned MaxKernArgAlign; + Align MaxKernArgAlign; HSACodeProps.mKernargSegmentSize = STM.getKernArgSegmentSize(F, MaxKernArgAlign); HSACodeProps.mGroupSegmentFixedSize = ProgramInfo.LDSSize; HSACodeProps.mPrivateSegmentFixedSize = ProgramInfo.ScratchSize; - HSACodeProps.mKernargSegmentAlign = std::max(MaxKernArgAlign, 4u); + HSACodeProps.mKernargSegmentAlign = + std::max(MaxKernArgAlign, Align(4)).value(); HSACodeProps.mWavefrontSize = STM.getWavefrontSize(); HSACodeProps.mNumSGPRs = ProgramInfo.NumSGPR; HSACodeProps.mNumVGPRs = ProgramInfo.NumVGPR; @@ -883,7 +884,7 @@ MetadataStreamerV3::getHSAKernelProps(const MachineFunction &MF, auto Kern = HSAMetadataDoc->getMapNode(); - unsigned MaxKernArgAlign; + Align MaxKernArgAlign; Kern[".kernarg_segment_size"] = Kern.getDocument()->getNode( STM.getKernArgSegmentSize(F, MaxKernArgAlign)); Kern[".group_segment_fixed_size"] = @@ -891,7 +892,7 @@ MetadataStreamerV3::getHSAKernelProps(const MachineFunction &MF, Kern[".private_segment_fixed_size"] = Kern.getDocument()->getNode(ProgramInfo.ScratchSize); Kern[".kernarg_segment_align"] = - Kern.getDocument()->getNode(std::max(uint32_t(4), MaxKernArgAlign)); + Kern.getDocument()->getNode(std::max(Align(4), MaxKernArgAlign).value()); Kern[".wavefront_size"] = Kern.getDocument()->getNode(STM.getWavefrontSize()); Kern[".sgpr_count"] = Kern.getDocument()->getNode(ProgramInfo.NumSGPR); diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index c299e38b363..8b31cbe1780 100644 --- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -4165,7 +4165,7 @@ uint32_t AMDGPUTargetLowering::getImplicitParameterOffset( const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(getTargetMachine(), MF.getFunction()); unsigned ExplicitArgOffset = ST.getExplicitKernelArgOffset(MF.getFunction()); - unsigned Alignment = ST.getAlignmentForImplicitArgPtr(); + const Align Alignment = ST.getAlignmentForImplicitArgPtr(); uint64_t ArgOffset = alignTo(MFI->getExplicitKernArgSize(), Alignment) + ExplicitArgOffset; switch (Param) { diff --git a/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp b/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp index 5dd5b3691e0..e64542a395f 100644 --- a/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp +++ b/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp @@ -72,10 +72,10 @@ bool AMDGPULowerKernelArguments::runOnFunction(Function &F) { BasicBlock &EntryBlock = *F.begin(); IRBuilder<> Builder(&*EntryBlock.begin()); - const unsigned KernArgBaseAlign = 16; // FIXME: Increase if necessary + const Align KernArgBaseAlign(16); // FIXME: Increase if necessary const uint64_t BaseOffset = ST.getExplicitKernelArgOffset(F); - unsigned MaxAlign; + Align MaxAlign; // FIXME: Alignment is broken broken with explicit arg offset.; const uint64_t TotalKernArgSize = ST.getKernArgSegmentSize(F, MaxAlign); if (TotalKernArgSize == 0) @@ -94,12 +94,12 @@ bool AMDGPULowerKernelArguments::runOnFunction(Function &F) { for (Argument &Arg : F.args()) { Type *ArgTy = Arg.getType(); - unsigned Align = DL.getABITypeAlignment(ArgTy); + unsigned ABITypeAlign = DL.getABITypeAlignment(ArgTy); unsigned Size = DL.getTypeSizeInBits(ArgTy); unsigned AllocSize = DL.getTypeAllocSize(ArgTy); - uint64_t EltOffset = alignTo(ExplicitArgOffset, Align) + BaseOffset; - ExplicitArgOffset = alignTo(ExplicitArgOffset, Align) + AllocSize; + uint64_t EltOffset = alignTo(ExplicitArgOffset, ABITypeAlign) + BaseOffset; + ExplicitArgOffset = alignTo(ExplicitArgOffset, ABITypeAlign) + AllocSize; if (Arg.use_empty()) continue; @@ -128,8 +128,8 @@ bool AMDGPULowerKernelArguments::runOnFunction(Function &F) { int64_t AlignDownOffset = alignDown(EltOffset, 4); int64_t OffsetDiff = EltOffset - AlignDownOffset; - unsigned AdjustedAlign = MinAlign(DoShiftOpt ? AlignDownOffset : EltOffset, - KernArgBaseAlign); + Align AdjustedAlign = commonAlignment( + KernArgBaseAlign, DoShiftOpt ? AlignDownOffset : EltOffset); Value *ArgPtr; Type *AdjustedArgTy; @@ -160,7 +160,7 @@ bool AMDGPULowerKernelArguments::runOnFunction(Function &F) { ArgPtr = Builder.CreateBitCast(ArgPtr, AdjustedArgTy->getPointerTo(AS), ArgPtr->getName() + ".cast"); LoadInst *Load = - Builder.CreateAlignedLoad(AdjustedArgTy, ArgPtr, AdjustedAlign); + Builder.CreateAlignedLoad(AdjustedArgTy, ArgPtr, AdjustedAlign.value()); Load->setMetadata(LLVMContext::MD_invariant_load, MDNode::get(Ctx, {})); MDBuilder MDB(Ctx); @@ -220,8 +220,8 @@ bool AMDGPULowerKernelArguments::runOnFunction(Function &F) { } KernArgSegment->addAttribute( - AttributeList::ReturnIndex, - Attribute::getWithAlignment(Ctx, std::max(KernArgBaseAlign, MaxAlign))); + AttributeList::ReturnIndex, + Attribute::getWithAlignment(Ctx, std::max(KernArgBaseAlign, MaxAlign))); return true; } diff --git a/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp b/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp index 0d3a1f1a769..89ca702f577 100644 --- a/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp +++ b/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp @@ -17,7 +17,6 @@ AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF) : MachineFunctionInfo(), LocalMemoryObjects(), ExplicitKernArgSize(0), - MaxKernArgAlign(0), LDSSize(0), IsEntryFunction(AMDGPU::isEntryFunctionCC(MF.getFunction().getCallingConv())), NoSignedZerosFPMath(MF.getTarget().Options.NoSignedZerosFPMath), diff --git a/lib/Target/AMDGPU/AMDGPUMachineFunction.h b/lib/Target/AMDGPU/AMDGPUMachineFunction.h index 52987e2fa41..9818ab1ef14 100644 --- a/lib/Target/AMDGPU/AMDGPUMachineFunction.h +++ b/lib/Target/AMDGPU/AMDGPUMachineFunction.h @@ -23,7 +23,7 @@ class AMDGPUMachineFunction : public MachineFunctionInfo { protected: uint64_t ExplicitKernArgSize; // Cache for this. - unsigned MaxKernArgAlign; // Cache for this. + Align MaxKernArgAlign; // Cache for this. /// Number of bytes in the LDS that are being used. unsigned LDSSize; @@ -47,9 +47,7 @@ public: return ExplicitKernArgSize; } - unsigned getMaxKernArgAlign() const { - return MaxKernArgAlign; - } + unsigned getMaxKernArgAlign() const { return MaxKernArgAlign.value(); } unsigned getLDSSize() const { return LDSSize; diff --git a/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index cf89af68d6f..3bb6dd4571c 100644 --- a/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -492,28 +492,28 @@ bool AMDGPUSubtarget::makeLIDRangeMetadata(Instruction *I) const { } uint64_t AMDGPUSubtarget::getExplicitKernArgSize(const Function &F, - unsigned &MaxAlign) const { + Align &MaxAlign) const { assert(F.getCallingConv() == CallingConv::AMDGPU_KERNEL || F.getCallingConv() == CallingConv::SPIR_KERNEL); const DataLayout &DL = F.getParent()->getDataLayout(); uint64_t ExplicitArgBytes = 0; - MaxAlign = 1; + MaxAlign = Align::None(); for (const Argument &Arg : F.args()) { Type *ArgTy = Arg.getType(); - unsigned Align = DL.getABITypeAlignment(ArgTy); + const Align Alignment(DL.getABITypeAlignment(ArgTy)); uint64_t AllocSize = DL.getTypeAllocSize(ArgTy); - ExplicitArgBytes = alignTo(ExplicitArgBytes, Align) + AllocSize; - MaxAlign = std::max(MaxAlign, Align); + ExplicitArgBytes = alignTo(ExplicitArgBytes, Alignment) + AllocSize; + MaxAlign = std::max(MaxAlign, Alignment); } return ExplicitArgBytes; } unsigned AMDGPUSubtarget::getKernArgSegmentSize(const Function &F, - unsigned &MaxAlign) const { + Align &MaxAlign) const { uint64_t ExplicitArgBytes = getExplicitKernArgSize(F, MaxAlign); unsigned ExplicitOffset = getExplicitKernelArgOffset(F); @@ -521,7 +521,7 @@ unsigned AMDGPUSubtarget::getKernArgSegmentSize(const Function &F, uint64_t TotalSize = ExplicitOffset + ExplicitArgBytes; unsigned ImplicitBytes = getImplicitArgNumBytes(F); if (ImplicitBytes != 0) { - unsigned Alignment = getAlignmentForImplicitArgPtr(); + const Align Alignment = getAlignmentForImplicitArgPtr(); TotalSize = alignTo(ExplicitArgBytes, Alignment) + ImplicitBytes; } diff --git a/lib/Target/AMDGPU/AMDGPUSubtarget.h b/lib/Target/AMDGPU/AMDGPUSubtarget.h index bf7cf86bc42..f5848aa8089 100644 --- a/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ b/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -196,8 +196,8 @@ public: return LocalMemorySize; } - unsigned getAlignmentForImplicitArgPtr() const { - return isAmdHsaOS() ? 8 : 4; + Align getAlignmentForImplicitArgPtr() const { + return isAmdHsaOS() ? Align(8) : Align(4); } /// Returns the offset in bytes from the start of the input buffer @@ -238,10 +238,8 @@ public: return 16; return AMDGPU::getIntegerAttribute(F, "amdgpu-implicitarg-num-bytes", 0); } - uint64_t getExplicitKernArgSize(const Function &F, - unsigned &MaxAlign) const; - unsigned getKernArgSegmentSize(const Function &F, - unsigned &MaxAlign) const; + uint64_t getExplicitKernArgSize(const Function &F, Align &MaxAlign) const; + unsigned getKernArgSegmentSize(const Function &F, Align &MaxAlign) const; virtual ~AMDGPUSubtarget() {} }; diff --git a/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 73115af3122..7dd0f11c95d 100644 --- a/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -501,7 +501,7 @@ void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) { bool SIMachineFunctionInfo::initializeBaseYamlFields( const yaml::SIMachineFunctionInfo &YamlMFI) { ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize; - MaxKernArgAlign = YamlMFI.MaxKernArgAlign; + MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign); LDSSize = YamlMFI.LDSSize; HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress; IsEntryFunction = YamlMFI.IsEntryFunction; diff --git a/lib/Transforms/IPO/Attributor.cpp b/lib/Transforms/IPO/Attributor.cpp index ce720e4aff7..73cf5ee4c9c 100644 --- a/lib/Transforms/IPO/Attributor.cpp +++ b/lib/Transforms/IPO/Attributor.cpp @@ -2745,7 +2745,8 @@ struct AAAlignImpl : AAAlign { getDeducedAttributes(LLVMContext &Ctx, SmallVectorImpl &Attrs) const override { if (getAssumedAlign() > 1) - Attrs.emplace_back(Attribute::getWithAlignment(Ctx, getAssumedAlign())); + Attrs.emplace_back( + Attribute::getWithAlignment(Ctx, Align(getAssumedAlign()))); } /// See AbstractAttribute::getAsStr(). diff --git a/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir index 8196933bc58..8334ef5ef6c 100644 --- a/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir +++ b/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir @@ -76,7 +76,7 @@ body: | # ALL-LABEL: name: no_mfi # FULL: machineFunctionInfo: # FULL-NEXT: explicitKernArgSize: 0 -# FULL-NEXT: maxKernArgAlign: 0 +# FULL-NEXT: maxKernArgAlign: 1 # FULL-NEXT: ldsSize: 0 # FULL-NEXT: isEntryFunction: false # FULL-NEXT: noSignedZerosFPMath: false @@ -96,6 +96,7 @@ body: | # FULL-NEXT: body: # SIMPLE: machineFunctionInfo: +# SIMPLE-NEXT: maxKernArgAlign: 1 # SIMPLE-NEXT: argumentInfo: # SIMPLE-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } # SIMPLE-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' } @@ -112,7 +113,7 @@ body: | # ALL-LABEL: name: empty_mfi # FULL: machineFunctionInfo: # FULL-NEXT: explicitKernArgSize: 0 -# FULL-NEXT: maxKernArgAlign: 0 +# FULL-NEXT: maxKernArgAlign: 1 # FULL-NEXT: ldsSize: 0 # FULL-NEXT: isEntryFunction: false # FULL-NEXT: noSignedZerosFPMath: false @@ -132,6 +133,7 @@ body: | # FULL-NEXT: body: # SIMPLE: machineFunctionInfo: +# SIMPLE-NEXT: maxKernArgAlign: 1 # SIMPLE-NEXT: argumentInfo: # SIMPLE-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } # SIMPLE-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' } @@ -149,7 +151,7 @@ body: | # ALL-LABEL: name: empty_mfi_entry_func # FULL: machineFunctionInfo: # FULL-NEXT: explicitKernArgSize: 0 -# FULL-NEXT: maxKernArgAlign: 0 +# FULL-NEXT: maxKernArgAlign: 1 # FULL-NEXT: ldsSize: 0 # FULL-NEXT: isEntryFunction: true # FULL-NEXT: noSignedZerosFPMath: false @@ -169,6 +171,7 @@ body: | # FULL-NEXT: body: # SIMPLE: machineFunctionInfo: +# SIMPLE-NEXT: maxKernArgAlign: 1 # SIMPLE-NEXT: isEntryFunction: true # SIMPLE-NEXT: argumentInfo: # SIMPLE-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } diff --git a/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/test/CodeGen/MIR/AMDGPU/machine-function-info.ll index 400c73fce9e..bc354f2a0d8 100644 --- a/test/CodeGen/MIR/AMDGPU/machine-function-info.ll +++ b/test/CodeGen/MIR/AMDGPU/machine-function-info.ll @@ -39,7 +39,7 @@ define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { ; CHECK-LABEL: {{^}}name: ps_shader ; CHECK: machineFunctionInfo: ; CHECK-NEXT: explicitKernArgSize: 0 -; CHECK-NEXT: maxKernArgAlign: 0 +; CHECK-NEXT: maxKernArgAlign: 1 ; CHECK-NEXT: ldsSize: 0 ; CHECK-NEXT: isEntryFunction: true ; CHECK-NEXT: noSignedZerosFPMath: false @@ -64,7 +64,7 @@ define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) { ; CHECK-LABEL: {{^}}name: function ; CHECK: machineFunctionInfo: ; CHECK-NEXT: explicitKernArgSize: 0 -; CHECK-NEXT: maxKernArgAlign: 0 +; CHECK-NEXT: maxKernArgAlign: 1 ; CHECK-NEXT: ldsSize: 0 ; CHECK-NEXT: isEntryFunction: false ; CHECK-NEXT: noSignedZerosFPMath: false @@ -89,7 +89,7 @@ define void @function() { ; CHECK-LABEL: {{^}}name: function_nsz ; CHECK: machineFunctionInfo: ; CHECK-NEXT: explicitKernArgSize: 0 -; CHECK-NEXT: maxKernArgAlign: 0 +; CHECK-NEXT: maxKernArgAlign: 1 ; CHECK-NEXT: ldsSize: 0 ; CHECK-NEXT: isEntryFunction: false ; CHECK-NEXT: noSignedZerosFPMath: true diff --git a/unittests/IR/AttributesTest.cpp b/unittests/IR/AttributesTest.cpp index 06da35aca57..60708c4f81e 100644 --- a/unittests/IR/AttributesTest.cpp +++ b/unittests/IR/AttributesTest.cpp @@ -70,8 +70,8 @@ TEST(Attributes, AddAttributes) { TEST(Attributes, RemoveAlign) { LLVMContext C; - Attribute AlignAttr = Attribute::getWithAlignment(C, 8); - Attribute StackAlignAttr = Attribute::getWithStackAlignment(C, 32); + Attribute AlignAttr = Attribute::getWithAlignment(C, Align(8)); + Attribute StackAlignAttr = Attribute::getWithStackAlignment(C, Align(32)); AttrBuilder B_align_readonly; B_align_readonly.addAttribute(AlignAttr); B_align_readonly.addAttribute(Attribute::ReadOnly); @@ -141,9 +141,9 @@ TEST(Attributes, AddMatchingAlignAttr) { LLVMContext C; AttributeList AL; AL = AL.addAttribute(C, AttributeList::FirstArgIndex, - Attribute::getWithAlignment(C, 8)); + Attribute::getWithAlignment(C, Align(8))); AL = AL.addAttribute(C, AttributeList::FirstArgIndex + 1, - Attribute::getWithAlignment(C, 32)); + Attribute::getWithAlignment(C, Align(32))); EXPECT_EQ(8U, AL.getParamAlignment(0)); EXPECT_EQ(32U, AL.getParamAlignment(1)); -- 2.40.0