From b5762155f70de5b4552866d2e1aa906b427e0521 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Fri, 29 Mar 2019 18:22:18 +0000
Subject: [PATCH] [MIPS] Regenerate double constant comparison test

Prep work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357294 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/Mips/2013-11-18-fp64-const0.ll | 55 +++++++++++++++++----
 1 file changed, 45 insertions(+), 10 deletions(-)

diff --git a/test/CodeGen/Mips/2013-11-18-fp64-const0.ll b/test/CodeGen/Mips/2013-11-18-fp64-const0.ll
index 6a210a0c76c..8e8746d59ef 100644
--- a/test/CodeGen/Mips/2013-11-18-fp64-const0.ll
+++ b/test/CodeGen/Mips/2013-11-18-fp64-const0.ll
@@ -1,5 +1,6 @@
-; RUN: llc -march=mips -mattr=-fp64 < %s | FileCheck -check-prefix=CHECK-FP32 %s
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefix=CHECK-FP64 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=mips-- -mattr=-fp64 | FileCheck %s -check-prefix=CHECK-FP32
+; RUN: llc < %s -mtriple=mips-- -mcpu=mips32r2 -mattr=+fp64 | FileCheck %s -check-prefix=CHECK-FP64
 
 ; This test case is a simplified version of an llvm-stress generated test with
 ; seed=3718491962.
@@ -8,16 +9,50 @@
 ; This was caused by impossible register class restrictions caused by the use
 ; of BuildPairF64 instead of BuildPairF64_64.
 
+; FIXME: A redundant mthc1 is currently emitted.
 define void @autogen_SD3718491962() {
+; CHECK-FP32-LABEL: autogen_SD3718491962:
+; CHECK-FP32:       # %bb.0: # %BB
+; CHECK-FP32-NEXT:    lui $1, %hi($CPI0_0)
+; CHECK-FP32-NEXT:    ldc1 $f0, %lo($CPI0_0)($1)
+; CHECK-FP32-NEXT:    mtc1 $zero, $f2
+; CHECK-FP32-NEXT:    mtc1 $zero, $f3
+; CHECK-FP32-NEXT:  $BB0_1: # %CF88
+; CHECK-FP32-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-FP32-NEXT:    c.ueq.d $f0, $f0
+; CHECK-FP32-NEXT:    addiu $1, $zero, 1
+; CHECK-FP32-NEXT:    movf $1, $zero, $fcc0
+; CHECK-FP32-NEXT:    c.olt.d $f0, $f2
+; CHECK-FP32-NEXT:    addiu $2, $zero, 1
+; CHECK-FP32-NEXT:    movt $2, $zero, $fcc0
+; CHECK-FP32-NEXT:    and $1, $2, $1
+; CHECK-FP32-NEXT:    bnez $1, $BB0_1
+; CHECK-FP32-NEXT:    nop
+; CHECK-FP32-NEXT:  # %bb.2: # %CF85
+; CHECK-FP32-NEXT:    jr $ra
+; CHECK-FP32-NEXT:    nop
+;
+; CHECK-FP64-LABEL: autogen_SD3718491962:
+; CHECK-FP64:       # %bb.0: # %BB
+; CHECK-FP64-NEXT:    lui $1, %hi($CPI0_0)
+; CHECK-FP64-NEXT:    ldc1 $f0, %lo($CPI0_0)($1)
+; CHECK-FP64-NEXT:    mtc1 $zero, $f1
+; CHECK-FP64-NEXT:    mthc1 $zero, $f1
+; CHECK-FP64-NEXT:  $BB0_1: # %CF88
+; CHECK-FP64-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-FP64-NEXT:    c.ueq.d $f0, $f0
+; CHECK-FP64-NEXT:    addiu $1, $zero, 1
+; CHECK-FP64-NEXT:    movf $1, $zero, $fcc0
+; CHECK-FP64-NEXT:    c.olt.d $f0, $f1
+; CHECK-FP64-NEXT:    addiu $2, $zero, 1
+; CHECK-FP64-NEXT:    movt $2, $zero, $fcc0
+; CHECK-FP64-NEXT:    and $1, $2, $1
+; CHECK-FP64-NEXT:    bnez $1, $BB0_1
+; CHECK-FP64-NEXT:    nop
+; CHECK-FP64-NEXT:  # %bb.2: # %CF85
+; CHECK-FP64-NEXT:    jr $ra
+; CHECK-FP64-NEXT:    nop
 BB:
-  ; CHECK-FP32: mtc1 $zero, $f{{[0-3]*[02468]}}
-  ; CHECK-FP32: mtc1 $zero, $f{{[0-3]*[13579]}}
-
-  ; CHECK-FP64: mtc1 $zero, $f{{[0-9]+}}
-  ; CHECK-FP64-NOT: mtc1 $zero,
-  ; FIXME: A redundant mthc1 is currently emitted. Add a -NOT when it is
-  ;        eliminated
-
   %Cmp = fcmp ule double 0.000000e+00, undef
   %Cmp11 = fcmp ueq double 0xFDBD965CF1BB7FDA, undef
   br label %CF88
-- 
2.50.1