From b20675f79611e79fd1d2a63e77b013718af35aef Mon Sep 17 00:00:00 2001 From: Javed Absar Date: Fri, 4 Aug 2017 17:10:11 +0000 Subject: [PATCH] [ARM] Use searchable-table for banked registers This is a continuation of https://reviews.llvm.org/D36219 This patch uses reverse mapping (encoding->name) in ARMInstPrinter::printBankedRegOperand to get rid of hard-coded values (as pointed out by @olista01). Reviewed by: @fhahn, @rovka, @olista01 Differential Revision: https://reviews.llvm.org/D36260 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310072 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 50 +++---------------- 1 file changed, 6 insertions(+), 44 deletions(-) diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index e3002e29d0c..be6815af2eb 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -873,51 +873,13 @@ void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { uint32_t Banked = MI->getOperand(OpNum).getImm(); - uint32_t R = (Banked & 0x20) >> 5; - uint32_t SysM = Banked & 0x1f; - - // Nothing much we can do about this, the encodings are specified in B9.2.3 of - // the ARM ARM v7C, and are all over the shop. - if (R) { - O << "SPSR_"; - - switch (SysM) { - case 0x0e: - O << "fiq"; - return; - case 0x10: - O << "irq"; - return; - case 0x12: - O << "svc"; - return; - case 0x14: - O << "abt"; - return; - case 0x16: - O << "und"; - return; - case 0x1c: - O << "mon"; - return; - case 0x1e: - O << "hyp"; - return; - default: - llvm_unreachable("Invalid banked SPSR register"); - } - } - - assert(!R && "should have dealt with SPSR regs"); - const char *RegNames[] = { - "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr", - "", "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", - "lr_fiq", "", "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt", - "sp_abt", "lr_und", "sp_und", "", "", "", "", - "lr_mon", "sp_mon", "elr_hyp", "sp_hyp"}; - const char *Name = RegNames[SysM]; - assert(Name[0] && "invalid banked register operand"); + auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked); + assert(TheReg && "invalid banked register operand"); + std::string Name = TheReg->Name; + uint32_t isSPSR = (Banked & 0x20) >> 5; + if (isSPSR) + Name.replace(0, 4, "SPSR"); // convert 'spsr_' to 'SPSR_' O << Name; } -- 2.50.1